VAST STOCK CO., LIMITED Datasheets for Supervisory Circuits and Battery Monitor Chips
Supervisory circuits and battery monitor chips are semiconductor devices that detect and monitor voltage levels in power supplies, microprocessors, and other systems.
Supervisory Circuits and Battery Monitor Chips: Learn more
| Product Name | Notes |
|---|---|
| Battery Management 5.8V OVP LiFePO4 BC SNG cell,3.6V Regula | |
| Battery Management Battery Cell Controller, Advanced, 14 Channels, SPI, LQFP64, reel | |
| Battery Management Battery Cell Controller, Advanced, 14 Channels, TPL, LQFP64, reel | |
| Battery Management Battery Cell Controller, Premium, 14 Channels, TPL, LQFP64, reel | |
| Battery Management Battery Cell Controller, Premium, 8 Channels, SPI, LQFP64, reel | |
| Battery Management Battery Managment IC, 4 channels, SPI communication, Advanced, LQFP 48 | |
| Battery Management Battery Managment IC, 4 channels, SPI communication, Premium, LQFP 48 | |
| Battery Management Battery Managment IC, 6 channels, TPL communication, Advanced, LQFP 48 | |
| Battery Management OVP BATTERY CHARGER DUAL CELL | |
| Battery Management Single cell OVP battery Charger | |
| Battery Management Single cell, 6.5V OVP LiFePO4 battery charger, 3.6V regulation | |
| Supervisory Circuits 1uA Sup P-P Act Low | |
| Supervisory Circuits 1uA Sup Push-Pull Act Low | |
| Supervisory Circuits 2.65V UnderVoltage Sensing Circuit | |
| Supervisory Circuits 4.27V UnderVoltage Sensing Circuit | |
| Supervisory Circuits 4.59V UnderVoltage Sensing Circuit | |
| Supervisory Circuits Act low OD Act high P-P | |
| Supervisory Circuits Act low P-P Act high P-P | |
| Supervisory Circuits Active high P-P, WDI, MR (WDI = 1600ms, reset delay = 200ms, Vtrpd - 3.1V) | |
| Supervisory Circuits Active high P-P, WDI, MR (WDI = 6.3ms, reset delay = 1.6ms, Vtrpd - 3.1V) | |
| Supervisory Circuits Active high P-P | |
| Supervisory Circuits ACTIVE LO OPEN DRAIN W/INT 4.7K PULL UP | |
| Supervisory Circuits ACTIVE LO OPEN-DRAIN WDI | |
| Supervisory Circuits ACTIVE LO/HI O-D P-P WDI | |
| Supervisory Circuits ACTIVE LO/HI O-D PP | |
| Supervisory Circuits Active low OD | |
| Supervisory Circuits Active low Open-drain + Active high P-P, WDI (WDI = 102ms, reset delay = 1.6ms, Vtrpd - 4.3V) | |
| Supervisory Circuits Active low Open-drain + Active high P-P, WDI (WDI = 102ms, reset delay = 30ms, Vtrpd - 2.9V) | |
| Supervisory Circuits Active low Open-drain + Active high P-P, WDI (WDI = 1600ms, reset delay = 1.6ms, Vtrpd - 2.9V) | |
| Supervisory Circuits Active low Open-drain + Active high P-P, WDI (WDI = 1600ms, reset delay = 1600ms, Vtrpd - 2.0V) | |
| Supervisory Circuits Active low Open-drain + Active high P-P, WDI (WDI = 1600ms, reset delay = 200ms, Vtrpd - 2.0V) | |
| Supervisory Circuits Active low Open-drain + Active high P-P, WDI (WDI = 1600ms, reset delay = 200ms, Vtrpd - 3.0V) | |
| Supervisory Circuits Active low Open-drain + Active high P-P, WDI (WDI = 1600ms, reset delay = 200ms, Vtrpd - 3.1V) | |
| Supervisory Circuits Active low Open-drain + Active high P-P, WDI (WDI = 1600ms, reset delay = 30ms, Vtrpd - 2.6V) | |
| Supervisory Circuits Active low Open-drain + Active high P-P, WDI (WDI = 25600ms, reset delay = 1.6ms, Vtrpd - 2.9V) | |
| Supervisory Circuits Active low Open-drain + Active high P-P, WDI (WDI = 6.3ms, reset delay = 1.6ms, Vtrpd - 2.9V) | |
| Supervisory Circuits Active low Open-drain + Active High-PP, MR(Reset delay = 1.6ms, Vtrpd - 2.9V) | |
| Supervisory Circuits Active low Open-drain + Active High-PP, MR(Reset delay = 200ms, Vtrpd - 2.7V) | |
| Supervisory Circuits Active low Open-drain + Active High-PP, MR(Reset delay = 30ms, Vtrpd - 3.1V) | |
| Supervisory Circuits Active low Open-Drain with Internal 4.7k Pull-up, WDI, MR (WDI = 1600ms, reset delay = 1.6ms, Vtrpd -2.6V) | |
| Supervisory Circuits Active low Open-Drain with Internal 4.7k Pull-up, WDI, MR (WDI = 1600ms, reset delay = 200ms, Vtrpd - 2.0V) | |
| Supervisory Circuits Active low Open-Drain with Internal 4.7k Pull-up, WDI, MR (WDI = 1600ms, reset delay = 200ms, Vtrpd - 2.3V) | |
| Supervisory Circuits Active low Open-Drain with Internal 4.7k Pull-up, WDI, MR (WDI = 1600ms, reset delay = 200ms, Vtrpd -3.1V) | |
| Supervisory Circuits Active low Open-Drain with Internal 4.7k Pull-up, WDI, MR (WDI = 1600ms, reset delay = 30ms, Vtrpd -4.5V) | |
| Supervisory Circuits Active low Open-Drain with Internal 4.7k Pull-up, WDI, MR (WDI = 25600ms, reset delay = 1600ms, Vtrpd - 2.0V) | |
| Supervisory Circuits Active low Open-drain with internal 4.7k pullup + Active high P-P, MR (Reset delay = 1600ms, Vtrpd - 2.4V) | |
| Supervisory Circuits Active low Open-drain with internal 4.7k pullup + Active high P-P, MR (Reset delay = 1600ms, Vtrpd - 4.7V) | |
| Supervisory Circuits Active low Open-drain with internal 4.7k pullup + Active high P-P, MR (Reset delay = 200ms, Vtrpd - 2.8V) | |
| Supervisory Circuits Active low Open-drain with internal 4.7k pullup + Active high P-P, MR (Reset delay = 30ms, Vtrpd - 2.6V) | |
| Supervisory Circuits Active low Open-drain with internal 4.7k pullup + Active high P-P, MR (Reset delay = 30ms, Vtrpd - 3.0V) | |
| Supervisory Circuits Active low Open-drain with internal 4.7k pullup+ Active-high P-P, WDI (WDI =25600ms, reset delay = 200ms, Vtrpd - 4.6V) | |
| Supervisory Circuits Active low Open-drain, WDI, MR (WDI = 102ms, reset delay = 1.6ms, Vtrpd - 3.0V) | |
| Supervisory Circuits Active low Open-drain, WDI, MR (WDI = 102ms, reset delay = 1.6ms, Vtrpd - 4.6V) | |
| Supervisory Circuits Active low Open-drain, WDI, MR (WDI = 102ms, reset delay = 200ms, Vtrpd - 3.1V) | |
| Supervisory Circuits Active low Open-drain, WDI, MR (WDI = 102ms, reset delay = 30ms, Vtrpd - 3.0V) | |
| Supervisory Circuits Active low Open-drain, WDI, MR (WDI = 1600ms, reset delay = 200ms, Vtrpd - 2.5V) | |
| Supervisory Circuits Active low Open-drain, WDI, MR (WDI = 1600ms, reset delay = 200ms, Vtrpd - 3.0V) | |
| Supervisory Circuits Active low Open-drain, WDI, MR (WDI = 1600ms, reset delay = 200ms, Vtrpd - 3.1V) | |
| Supervisory Circuits Active low Open-drain, WDI, MR (WDI = 1600ms, reset delay = 200ms, Vtrpd - 4.1V) | |
| Supervisory Circuits Active low Open-drain, WDI, MR (WDI = 1600ms, reset delay = 30ms, Vtrpd - 2.9V) | |
| Supervisory Circuits Active low Open-drain, WDI, MR (WDI = 25600ms, reset delay = 1600ms, Vtrpd - 2.9V) | |
| Supervisory Circuits Active low Open-drain, WDI, MR (WDI = 25600ms, reset delay = 200ms, Vtrpd - 2.7V) | |
| Supervisory Circuits Active low Open-drain, WDI, MR (WDI = 25600ms, reset delay = 30ms, Vtrpd - 1.9V) | |
| Supervisory Circuits Active low Open-drain, WDI, MR (WDI = 6.3ms, reset delay = 200ms, Vtrpd - 4.2V) | |
| Supervisory Circuits Active low Open-drain, WDI, MR (WDI = 6.3ms, reset delay = 30ms, Vtrpd - 4.2V) | |
| Supervisory Circuits Active low P-P + Active high P-P, MR(Reset delay = 1.6ms, Vtrpd - 4.4V) | |
| Supervisory Circuits Active low P-P + Active high P-P, MR(Reset delay = 200ms, Vtrpd - 2.8V) | |
| Supervisory Circuits Active low P-P + Active high P-P, MR(Reset delay = 200ms, Vtrpd - 2.9V) | |
| Supervisory Circuits ACTIVE LOW P-P WDI | |
| Supervisory Circuits Active low P-P, WDI, MR (WDI = 102ms, reset delay = 200ms, Vtrpd - 4.6V) | |
| Supervisory Circuits Active low P-P, WDI, MR (WDI = 102ms, reset delay = 30ms, Vtrpd - 3.0V) | |
| Supervisory Circuits Active low P-P, WDI, MR (WDI = 102ms, reset delay = 30ms, Vtrpd - 4.7V) | |
| Supervisory Circuits Active low P-P, WDI, MR (WDI = 1600ms, reset delay = 1.6ms, Vtrpd - 3.0V) | |
| Supervisory Circuits Active low P-P, WDI, MR (WDI = 1600ms, reset delay = 1.6ms, Vtrpd - 4.6V) | |
| Supervisory Circuits Active low P-P, WDI, MR (WDI = 1600ms, reset delay = 200ms, Vtrpd - 2.0V) | |
| Supervisory Circuits Active low P-P, WDI, MR (WDI = 1600ms, reset delay = 200ms, Vtrpd - 2.3V) | |
| Supervisory Circuits Active low P-P, WDI, MR (WDI = 1600ms, reset delay = 200ms, Vtrpd - 2.6V) | |
| Supervisory Circuits Active low P-P, WDI, MR (WDI = 1600ms, reset delay = 200ms, Vtrpd - 2.7V) | |
| Supervisory Circuits Active low P-P, WDI, MR (WDI = 1600ms, reset delay = 200ms, Vtrpd - 3.1V) | |
| Supervisory Circuits Active low P-P, WDI, MR (WDI = 1600ms, reset delay = 200ms, Vtrpd - 3.2V) | |
| Supervisory Circuits Active low P-P, WDI, MR (WDI = 1600ms, reset delay = 200ms, Vtrpd - 4.4V) | |
| Supervisory Circuits Active low P-P, WDI, MR (WDI = 25600ms, reset delay = 200ms, Vtrpd - 2.5V) | |
| Supervisory Circuits Active low P-P, WDI, MR (WDI = 6.3ms, reset delay = 1600ms, Vtrpd - 4.4V) | |
| Supervisory Circuits Active low P-P, WDI, MR (WDI = 6.3ms, reset delay = 200ms, Vtrpd - 2.6V) | |
| Supervisory Circuits Active low P-P, WDI, MR (WDI = 6.3ms, reset delay = 200ms, Vtrpd - 4.4V) | |
| Supervisory Circuits Active low P-P | |
| Supervisory Circuits ACTIVE LOW/HIGH P-P WDI | |
| Supervisory Circuits ANA UNDER 5V SENSE CRKT | |
| Supervisory Circuits Open Drain Low | |
| Supervisory Circuits Open Drain | |
| Supervisory Circuits Push-Pull High | |
| Supervisory Circuits Push-Pull Low | |
| Supervisory Circuits Universal Voltage Monitor | |
| Supervisory Circuits w/5K Pull-Up Low | |
| Supervisory Circuits WDI Active Lo P-P Active HI P-P | |
| Supervisory Circuits |
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