Accuris Datasheets for Standards and Technical Documents
Standards and technical documents includes standards, codes, regulation, handbooks, manuals, comprehensive guides and other formal publications. Standards, codes, and regulation establish uniform specifications, procedures or technical criteria.
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| Product Name | Notes |
|---|---|
| 3D Chip Stack with Through-Silicon Vias (TSVS): Identifying, Evaluating and Understanding Reliability Interactions | |
| A Case for Lowering Component-level CDM ESD Specifications and Requirements Part II: Die-to-Die Interfaces | |
| A Guideline for Defining \x93Low-Halogen\x94 Solid State Devices (Removal of BFR/CFR/PVC) | |
| Accelerated Moisture Resistance - Unbiased Autoclave (Revision of Test Method A102-A - Previously Published in JESD22) | |
| Accelerated Moisture Resistance - Unbiased Autoclave | |
| Accelerated Moisture Resistance - Unbiased HAST | |
| ADAPTER TEST BOARD RELIABILITY TEST GUIDELINES | |
| Addendum No. 1 to JESD251, Optional x4 Quad I/O With Data Strobe | |
| Alpha Radiation Measurement in Electronic Materials | |
| Application Thermal Derating Methodologies | |
| Assessment of Average Outgoing Quality Levels in Parts Per Million (PPM) | |
| Assessment of Microcircuit Outgoing Quality Levels in Parts per Million (PPM) | |
| Avalanche Breakdown Diode (ABD) Transient Voltage Suppressors | |
| Beaded Thermocouple Temperature Measurement of Semiconductor Packages | |
| BGA Ball Shear | |
| Bias Life (Revision of Test Method A108 - Previously Published in JESD22) | |
| Board Level Cyclic Bend Test Method for Interconnect Reliability Characterization of Components for Handheld Electronic Products | |
| Board Level Cyclic Bend Test Method for Interconnect Reliability Characterization of SMT ICs for Handheld Electronic Products | |
| Board Level Drop Test Method of Components for Handheld Electronic Products | |
| Byte Addressable Energy Backed Interface | |
| Ceramic Package Specification for Microelectronic Packages | |
| Characterization and Monitoring of Thermal Stress Test Oven Temperatures | |
| Characterization of Interfacial Adhesion in Semiconductor Packages | |
| Chip Carrier Pinouts Standardized for CMOS 4000, HC and HCT Series of Logic Circuits | |
| Chip-Package Interaction Understanding, Identification and Evaluation | |
| Chip-Package Interaction Understanding, Identification, and Evaluation | |
| CMOS Gate Array Macrocell Standard | |
| CMOS SEMICUSTOM INTEGRATED CIRCUITS | |
| Color Coding of Discrete Semiconductor Devices | |
| Common Flash Interface (CFI) ID Codes | |
| Common Test Method for Detecting Component Surface Finish Materials | |
| Commutating Diode Safe Operating Area Test Procedure for Measuring dv/dt During Reverse Recovery of Power Transistors | |
| Compact Thermal Model Overview | |
| Configurations for Solid State Memories | |
| Constant Temperature Aging to Characterize Aluminum Interconnect Metallization for Stress-Induced Voiding | |
| Constant-Temperature Aging Method to Characterize Copper Interconnect Metallization for Stress-Induced Voiding | |
| Coplanarity Test for Surface-Mount Semiconductor Devices | |
| Counterfeit Electronic Parts: Non-Proliferation for Manufacturers | |
| Customer Notification Process for Disasters | |
| Cycled Temperature-Humidity -Bias Life Test | |
| Cycled Temperature-Humidity -Bias with Surface Condensation Life Test | |
| DDR2 DIMM Clock Skew Measurement Procedure Using A Clock Reference Board | |
| DDR4 NVDIMM-N Design Specification | |
| DDR4 NVDIMM-N Design Standard Revision 1.0 | |
| DDR4 NVDIMM-N Design Standard | |
| DDR4 PROTOCOL CHECKS | |
| DELPHI Compact Thermal Model Guideline | |
| Description of "B" Series CMOS Devices, Spec. for | |
| Design for Testability Guidelines | |
| Digital Bipolar Pinouts for Chip Carriers | |
| Discontinuing Use of the Machine Model for Device ESD Qualification | |
| Dynamic ON-Resistance Test Method Guidelines for GaN HEMT based Power Conversion Devices | |
| ECXML Guidelines for Electronic Thermal System Level Models \x96 XML Requirements | |
| Electrically Erasable Programmable ROM (EEPROM) Program / Erase Endurance and Data Retention Stress Test | |
| Electrically Erasable Programmable ROM (EEPROM) Program/Erase Endurance and Data Retention Stress Test | |
| Electrically Erasable Programmable ROM (EEPROM) Program/Erase Endurance and Data Retention Test | |
| Electrostatic Discharge (ESD) Sensitivity Testing \x96 Reporting ESD Withstand Levels on Datasheets | |
| Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM) | |
| Electrostatic Discharge (ESD) Sensitivity Testing, Machine Model (MM) | |
| Embedded Multimediacard (eMMC) Security Extension | |
| Enclosure Form Factor for SSD Devices, Version 1.0 | |
| Environmental Acceptance Requirements for Tin Whisker Susceptibility of Tin and Tin Alloy Surface Finishes | |
| Evaluation Procedure for Determining Capability to Bottom Side Board Attach by Full Body Solder Immersion of Small Surface Mount Solid State Devices | |
| EXpanded Serial Peripheral Interface (xSPI) for Non Volatile Memory Devices, Version 1.0 | |
| EXpanded Serial Peripheral Interface (xSPI) for Non Volatile Memory Devices | |
| External Visual | |
| FBDIMM Specification: DDR2 SDRAM Fully Buffered DIMM (FBDIMM) Design Specification | |
| FBDIMM: Architecture and Protocol | |
| Field-Induced Charged-Device Model Test Method for Electrostatic- Discharge-Withstand Thresholds of Microelectronic Components | |
| Field-Induced Charged-Device Model Test Method for Electrostatic-Discha rge-Withstand Thresholds of Microelectronic Components | |
| Flip Chip Tensile Pull | |
| Gate Charge Test Method | |
| GDDR5 Measurement Procedures | |
| GDDR5 SGRAM | |
| General Specification for Plastic Encapsulated Microcircuits for Use in Rugged Applications | |
| GRAPHICS DOUBLE DATA RATE (GDDR5) SGRAM STANDARD | |
| GRAPHICS DOUBLE DATA RATE (GDDR5X) SGRAM STANDARD | |
| GRAPHICS DOUBLE DATA RATE (GDDR6) SGRAM STANDARD | |
| Graphics Double Data Rate 7 SGRAM Standard (GDDR7) | |
| Guide for the Production and Acquisition of Radiation-Hardness Assured Multichip Modules and Hybrid Microcircuits | |
| Guide for the Production and Acquisition of Radiation-Hardness- Assured Multichip Modules and Hybrid Microcircuits | |
| Guide to Standards and Publications Relating to Quality and Reliability of Electronic Hardware | |
| Guideline for Assessing the Current-Carrying Capability of the Leads in a Power Package System | |
| Guideline for Characterizing Solder Bump Electromigration under Constant Current and Temperature Stress | |
| Guideline for evaluating Bias Temperature Instability of Silicon Carbide Metal-Oxide-Semicond uctor Devices for Power Electronic Conversion | |
| Guideline for Evaluating Bipolar Degradation of Silicon Carbide Power Devices | |
| Guideline for Evaluating Gate Switching Instability of Silicon Carbide Metal-Oxide-Semicond uctor Devices for Power Electronic Conversion | |
| Guideline for Gate Oxide Reliability and Robustness Evaluation Procedures for Silicon Carbide Power MOSFETs | |
| Guideline for Internal Gas Analysis for Microelectronic Packages | |
| Guideline for Residual Gas Analysis (RGA) for Microelectronic Packages | |
| Guideline for Reverse Bias Reliability Evaluation Procedures for Gallium Nitride Power Conversion Devices | |
| Guideline for Switching Reliability Evaluation Procedures for Gallium Nitride Power Conversion Devices Version 1.0 | |
| Guideline for Switching Reliability Evaluation Procedures for Gallium Nitride Power Conversion Devices | |
| Guideline to Specify a Transient Off-State Withstand Voltage Robustness Indicator in Datasheets for Lateral GaN Power Conversion Devices, Version 1.0 | |
| Guidelines for Gate Charge (QG) Test Method for SiC MOSFET | |
| Guidelines for Measuring the Threshold Voltage (VT) of SiC MOSFETs | |
| Guidelines for Nondestructive Pull Testing of Wire Bonds on Hybrid Devices | |
| Guidelines for Preparing Customer-Supplied Background Information Relating to a Semiconductor-Device Failure Analysis | |
| Guidelines for Representing Switching Losses of SIC Mosfets in Datasheets | |
| Guidelines for Representing Threshold Voltage of SiC MOSFETs in Datasheets | |
| Guidelines for Reverse Recovery Time and Charge Measurement of SiC MOSFET | |
| Guidelines for Supplier Performance Rating | |
| Guidelines for Visual Inspection and Control of Flip Chip Type Components (FCxGA) | |
| Guidelines for Visual Inspection and Control of Flip Chip Type Packages (FCxGA) | |
| Hermeticity | |
| High Bandwidth Memory (HBM) DRAM | |
| High Bandwidth Memory DRAM (HBM1, HBM2) | |
| High Bandwidth Memory DRAM (HBM3) | |
| High Temperature Continuity | |
| High Temperature Package Warpage Measurement Methodology | |
| High Temperature Storage Life | |
| Highly Accelerated Temperature and Humidity Stress Test (HAST) | |
| Highly-Accelerated Temperature and Humidity Stress Test (HAST) | |
| Interface Standard for Semicustom Integrated Circuits | |
| JC-42.6 Manufacturer Identification (ID) Code for Low Power Memories | |
| Latch-up in CMOS Integrated Circuits | |
| Lead Integrity | |
| Leadless Chip Carrier Pinouts Standardized for Linear's | |
| Life Test Methods for Photoconductive Cells | |
| Long-Term Storage for Electronic Solid-State Wafers, Dice, and Devices | |
| Low Frequency Power Transistors | |
| Low Power Double Data Rate (LPDDR) 5/5X | |
| Low Power Double Data Rate (LPDDR) SDRAM Specification | |
| Low Power Double Data Rate (LPDDR) SDRAM Standard | |
| Low Power Double Data Rate (LPDDR) SDRAM, 1.2 V I/O | |
| Low Power Double Data Rate 2 (LPDDR2) | |
| Low Power Double Data Rate 3 (LPDDR3) | |
| Low Power Double Data Rate 4 (LPDDR4) | |
| Low Power Double Data Rate 4X (LPDDR4X) | |
| Low Power Double Data Rate 5 (LPDDR5) | |
| Low Power Double Date Rate 4 (LPDDR4) | |
| Low Temperature Storage Life | |
| LPDDR6 Standard | |
| Mark Legibility | |
| Mark Permanency | |
| Marking Permanency | |
| Measurement of Small-Signal Transistor Scattering Parameters | |
| Measuring Whisker Growth on Tin and Tin Alloy Surface Finishes | |
| Mechanical Compressive Static Stress Test Method | |
| Mechanical Shock \x96 Component and Subassembly | |
| Mechanical Shock \x96 Device and Subassembly | |
| Mechanical Shock | |
| Method for Characterizing the Electromigration Failure Time Distribution of Interconnects Under Constant-Current and Temperature Stress | |
| Method for Measurement of Power Device Turn-Off Switching Loss | |
| Method for Repetitive Inductive Load Avalanche Switching | |
| Method of Specification of Performance Parameters for CMOS Semicustom Integrated Circuits | |
| MICROELECTRONIC DEVICE TYPE ASSIGNMENTS | |
| Multi-wire Multi-level I/O Standard | |
| NAND Flash Interface Interoperability | |
| NEAR-TERM DRAM LEVEL ROWHAMMER MITIGATION | |
| Obtaining and Accepting Material for Use in Hybrid/MCM Products | |
| Package Warpage Measurement of Surface-Mount Integrated Circuits at Elevated Temperature | |
| Physical Dimensions | |
| Power and Temperature Cycling | |
| Power Cycling | |
| Power MOSFET Equivalent Series Gate Resistance Test Method | |
| Power MOSFET's | |
| Preconditioning of Nonhermetic Surface Mount Devices Prior to Reliability Testing | |
| Preferred Lead Configurations for Field-Effect Transistors | |
| Procedure for Measuring Input Capacitance Using a Vector Network Analyzer (VNA) | |
| Procedure for Reliability Characterization of Metal-Insulator-Meta l Capacitors | |
| Procedure for the Evaluation of Low-k/Metal Inter/Intra-Level Dielectric Integrity | |
| Procedure for Wafer-Level DC Characterization of Bias Temperature Instabilities | |
| Process Characterization Guideline | |
| Quality and Reliability Standards and Publications | |
| Radio Front End - Baseband Digital Parallel (RBDP) Interface | |
| Recommend Practice for Measurement of Transistor Lead Temperature | |
| Recommended ESD Target Level for HBM Qualification | |
| Recommended ESD Target Levels for HBM/MM Qualification | |
| Recommended ESD-CDM Target Levels | |
| Recommended Practice for Measurement of Transistor Lead Temperature | |
| Relative Spectral Response Curves for Semiconductor Infrared Detectors | |
| Reliability Qualification of Power Amplifier Modules | |
| Reliability Qualification of Semiconductor Devices Based on Physics of Failure Risk and Opportunity Assessment | |
| Replay Protected Monotonic Counter (RPMC) for Serial Flash Devices | |
| Resistance to Solder Shock for Through-Hole Mounted Devices | |
| RF BIASED LIFE (RFBL) TEST METHOD | |
| Salt Atmosphere (Revision of Test Method A107 - Previously Published in JESD22-B) | |
| Salt Atmosphere | |
| Secure Serial Flash Bus Transactions | |
| Selection of Burn-In/Life Test Conditions and Critical Parameters for QML Microcircuits | |
| Semiconductor Power Control Modules | |
| Semiconductor Wafer and Die Backside External Visual Inspection | |
| Serial Flash Discoverable Parameters (SFDP) | |
| Serial Flash Reset Signaling Protocol | |
| Serial Interface for Data Converters | |
| Serial NOR Security Hardware Abstraction Layer | |
| Short Circuit Withstand Time Test Method | |
| Signature Analysis | |
| Single Pulse Unclamped Inductive Switching (UIS) Avalanche Test Method | |
| Solder Ball Pull | |
| Solder Ball Shear | |
| Solderability | |
| Solid State Products Registration List - This publication includes addenda from 1976 to August 1986. The purpose of this list is to determine release numbers (file numbers) for JEDEC Type... | |
| Solid State Reliability Assessment and Qualification Methodologies | |
| Solid-State Drive (SSD) Endurance Workloads | |
| Solid-State Drive (SSD) Requirements and Endurance Test Method | |
| Solid-State Reliability Assessment and Qualification Methodologies | |
| SPECIALITY DDR2-1066 SDRAM | |
| SPI Safety Extensions (CRC) for Non Volatile SPI Flash Memories (QPI and xSPI) | |
| Standard for Cell-Based Integrated Circuit Benchmark Set | |
| Standard for Description of 54/74ACXXXXX and 54/74ACTXXXXX Advanced High-Speed CMOS Devices | |
| Standard for Description of Fast CMOS TTL Compatible Logic | |
| Standard for Gate Array Benchmark Set | |
| Standard List of Values to Be Used in Power Transistor Device Registration and Minimum Differences for Discreteness of Registration | |
| Standard Test Loads For Dual - Supply Level Translation Devices | |
| Standard Test Method Utilizing X-Ray Fluorescence (XRF) for Analyzing Component Finishes and Solder Alloys to Determine Tin (Sn) \x96 Lead (Pb) Content | |
| Steady State Temperature Humidity Bias Life Test | |
| Steady-State Temperature Humidity Bias Life Test (Revision of Test Method A101 - Previously Published in JESD22-B) | |
| Steady-State Temperature Humidity Bias Life Test | |
| Steady-State Temperature-Humidity Bias Life Test | |
| Stress-Test-Driven Qualification of and Failure Mechanisms Associated with Assembled Solid State Surface- Mount Components | |
| Stress-Test-Driven Qualification of and Failure Mechanisms Associated with Assembled Solid State Surface-Mount Components | |
| Stress-Test-Driven Qualification of and Failure Mechanisms Associated with Assembled Solid State Surface-Mount Devices | |
| Subassembly Mechanical Shock | |
| Survey On Latch-Up Testing Practices and Recommendations for Improvements | |
| System Level ESD Part II: Implementation of Effective ESD Robust Designs | |
| System Level ESD Part III: Review of ESD Testing and Impact on System-Efficient ESD Design (SEED) | |
| SYSTEM LEVEL ROWHAMMER MITIGATION | |
| Temperature Cycling (Revision of Test Method A104 - Previously Published in JESD22-B) | |
| Temperature Cycling | |
| Temperature, Bias, and Operating Life | |
| Terms and Definitions for Gate Arrays and Cell-Based Digital Integrated Circuits | |
| Terms, Definitions, and Letter Symbols for Microcomputers, Microprocessors, and Memory Integrated Circuits | |
| Test Method A103-A High Temperature Storage Life (Revision of Test Method A103 Previously Published in JESD22-B) | |
| Test Method A105-B Power and Temperature Cycling | |
| Test Method A106-A Thermal Shock (Revision of Test Method A106 - Previously Published JESD22-B) | |
| Test Method A110 Highly-Accelerated Temperature and Humidity Stress Test (HAST) | |
| Test Method A110-B Highly-Accelerated Temperature and Humidity Stress Test (HAST) | |
| Test Method A112-A Moisture-Induced Stress Sensitivity for Plastic Surface Mount Devices | |
| Test Method A113-A Preconditioning of Plastic Surface Mount Devices Prior to Reliability Testing | |
| Test Method A114 Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM) | |
| Test Method A115 Electrostatic Discharge (ESD) Sensitivity Testing Machine Model (MM) | |
| Test Method A115-A Electrostatic Discharge (ESD) Sensitivity Testing Machine Model (MM) | |
| Test Method B101 External Visual (Previously Published in JESD22-B) | |
| Test Method B102-C Solderability | |
| Test Method B105-B Lead Integrity | |
| Test Method B106-B Resistance to Soldering Temperature for Through-Hole Mounted Devices | |
| Test Method B106C Resistance to Soldering Temperature for Through-Hole Mounted Devices | |
| Test Method B107-A Marking Permanency (Previously Published in JESD22-B) | |
| Test Method B116 Wire Bond Shear Test | |
| Test Method C101 Field-Induced Charged-Device Model Test Method for Electrostatic Discharge Withstand Thresholds of Microelectronic Components | |
| Test Method for Continuous-Switching Evaluation of Gallium Nitride Power Conversion Devices | |
| Test Method for Measurement of Reverse Recovery Time trr for Power MOSFET Drain-Source Diodes | |
| Test Method for Measuring Whisker Growth on Tin and Tin Alloy Surface Finishes | |
| Test Method for the Measurement of Moisture Diffusivity and Water Solubility in Organic Materials Used in Electronic Devices | |
| Test Method for the Measurement of Moisture Diffusivity and Water Solubility in Organic Materials Used in Integrated Circuits | |
| Test Method for Total Ionizing Dose (TID) from X-ray Exposure in Terrestrial Applications | |
| Test Methods and Character Designations for Liquid Crystal Devices | |
| Test Methods and Procedures for Solid State Devices Used in Transportation/Autom otive Applications | |
| Test Methods to Characterize Voiding in Pre-SMT Ball Grid Array Packages | |
| Test Procedure for the Measurement of Terrestrial Cosmic Ray Induced Destructive Effects in Power Semiconductor Devices | |
| TEST STANDARD FOR THE MEASUREMENT OF PROTON RADIATION SINGLE EVENT EFFECTS IN ELECTRONIC DEVICES | |
| Thermal Impedance Measurement for Insulated Gate Bipolar Transistors (Delta VCE(on) Method) | |
| Thermal Impedance Measurements for Bipolar Transistors (Delta Base-Emitter Voltage Method) | |
| Thermal Impedance Measurements for Insulated Gate Bipolar Transistors | |
| Thermal Impedance Measurements for Vertical Power MOSFETs (Delta Source-Drain Voltage Method) | |
| Thermal Modeling Overview | |
| Thermal Shock | |
| Transistor, Gallium Arsenide Power Fet, Generic Specification | |
| Two-Resistor Compact Thermal Model Guideline | |
| Understanding Electrical Overstress - EOS | |
| Universal Flash Storage (UFS 1.1) | |
| Universal Flash Storage (UFS) Card Extension Version 1.0 | |
| Universal Flash Storage (UFS) Card Extension Version 1.1 | |
| Universal Flash Storage (UFS) Card Extension Version 3.0 | |
| Universal Flash Storage (UFS) File Based Optimizations (FBO) Extension | |
| Universal Flash Storage (UFS) Host Controller Interface | |
| Universal Flash Storage (UFS) Host Performance Booster(HPB) Extension | |
| Universal Flash Storage (UFS) Security Extension | |
| Universal Flash Storage (UFS) Test | |
| Universal Flash Storage (UFS) Unified Memory Extension Version 1.1 | |
| Universal Flash Storage (UFS) Unified Memory Extention Version 1.0 | |
| Universal Flash Storage (UFS) | |
| Universal Flash Storage Host Controller Interface (UFSHCI), Unified Memory Extension Version 1.0 | |
| Universal Flash Storage Host Controller Interface (UFSHCI), Unified Memory Extension Version 1.1 | |
| Universal Flash Storage Host Controller Interface (UFSHCI) | |
| User Guidelines for IR Thermal Imaging Determination of Die Temperature | |
| Verification of Maximum Ratings of Power Transistors, Test Procedures for | |
| Vibration, Variable Frequency | |
| Wide I/O 2 (WideIO2) | |
| Wide I/O Single Data Rate (Wide I/O SDR) | |
| Wire Bond Pull Test Methods | |
| Wire Bond Shear Test Method | |
| XFM Device | |
| Zener and Voltage Regulator Diode Rating Verification and Characterization Testing | |
| Zoned Storage UFS |
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