Accuris Datasheets for Standards and Technical Documents
Standards and technical documents includes standards, codes, regulation, handbooks, manuals, comprehensive guides and other formal publications. Standards, codes, and regulation establish uniform specifications, procedures or technical criteria.
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| Product Name | Notes |
|---|---|
| 0.5 V Low Voltage Swing Terminated Logic (LVSTL05) | |
| 0.6 V Low Voltage Swing Terminated Logic (LVSTL06) | |
| 1.0 V +/- 0.1 V (Normal Range) and 0.7 V - 1.1 V (Wide Range) Power Supply Voltage and Interface Standard for Nonterminated Digital Integrated Circuits | |
| 1.0 V +/- 0.1 V (Normal Range) and 0.7 V - 1.1V (Wide Range) Power Supply Voltage and Interface Standard for Nonterminated Digital Integrated Circuits | |
| 1.2 V +/- 0.1V (Normal Range) and 0.8 - 1.3 V (Wide Range) Power Supply Voltage and Interface Standard for Nonterminated Digital Integrated Circuits | |
| 1.2 V HIGH-SPEED LVCMOS (HS_LVCMOS) INTERFACE | |
| 1.25 V DDR3U-800, DDR3U-1066, DDR3U-1333, and DDR3U-1600 | |
| 1.35 V DDR3L-800, DDR3L-1066, DDR3L-1333, and DDR3L-1600 | |
| 1.35 V DDR3L-800, DDR3L-1066, DDR3L-1333, DDR3L-1600, and DDR3L-1866 | |
| 1.5 V +/- 0.1 V (Normal Range) and 0.9 V - 1.6 V (Wide Range) Power Supply Voltage and Interface Standard for Nonterminated Digital Integrated Circuits | |
| 1.5 V +/- 0.1 V (Normal Range) and 0.9 V 1.6 V (Wide Range) Power Supply Voltage and Interface Standard for Nonterminated Digital integrated Circuits | |
| 1.5 V +/- 0.1 V (Normal Range) and 0.9 V \x96 1.6 V (Wide Range) Power Supply Voltage and Interface Standard for Nonterminated Digital Integrated Circuits | |
| 1.8 V (PLUS OR MINUS) 0.15 V (Normal Range), and 1.2 - 1.95 V (Wide Range) Power Supply Voltage and Interface Standard for Non-Terminated Digital Integrated Circuit | |
| 1.8 V HIGH-SPEED LVCMOS (HS_LVCMOS) INTERFACE | |
| 1.8 V Plus or Minus 0.15 V (Normal Range), and 1.2 - 1.95 V (Wide Range) Power Supply Voltage and Interface Standard for Non-Terminated Digital Integrated Circuit | |
| 2.5 V (PLUS OR MINUS) 0.2 V (Normal Range) and 1.8 V \x96 2.7 V (Wide Range) Power Supply Voltage and Interface Standard for Nonterminated Digital Integrated Circuits | |
| 2.5 V BiCMOS Logic Device Family Specification with 5 V Tolerant Inputs and Outputs | |
| 2.5V +/- 0.2V (Normal Range), and 1.8V to 2.7V (Wide Range) Power Supply Voltage and Interface Standard for Nonterminated Digital Integrated Circuit | |
| 300 mV Interface | |
| 3D Stacked DRAM | |
| 3D Stacked SDRAM | |
| 54/74HCXXXX and 54/74HCTXXXX High Speed CMOS Devices, Description of | |
| 7Standard for Description of 3867: 2.5 V, Dual 5-Bit, 2-Port, DDR FET Switch | |
| A Procedure for Measuring P-Channel MOSFET Hot-Carrier- Induced Degradation Under DC Stress | |
| A Procedure for Measuring P-Channel MOSFET Negative Bias Temperature Instabilities | |
| Addendum No. 1 to JESD79-3 - 1.35 V DDR3L-800, DDR3L-1066, DDR3L-1333, DDR3L-1600, and DDR3L-1866 | |
| Addendum No. 1 to JESD79-4, 3D Stacked DRAM | |
| Application Specific Qualification Using Knowledge Based Test Methodology | |
| Automotive Solid State Drive (SSD) Device Standard | |
| Backup Energy Module Standard for NVDIMM Memory Devices (BEM) | |
| Ball Grid Array Pinout for 1-, 2-, and 3-Bit Logic Functions | |
| Ball Grid Array Pinouts Standardized for 16, 18 and 20-Bit Logic Functions Using a 54 Ball Package | |
| Ball Grid Array Pinouts Standardized for 16-Bit Logic Functions | |
| Ball Grid Array Pinouts Standardized for 32-Bit Logic Functions | |
| Ball Grid Array Pinouts Standardized for 8-Bit Logic Functions | |
| Bond Wire Modeling Standard | |
| Bus Interconnect Logic (BIC) for 1.2 Volts | |
| Center-Tap-Terminate d (CTT) Low-Level, High- Speed Interface Standard for Digital Integrated Circuits | |
| Common Flash Interface (CFI) | |
| Component Problem Analysis and Corrective Action Requirements | |
| Component Quality Problem Analysis and Corrective Action Requirements (Including Administrative Quality Problems) | |
| Compression Attached Memory Module (CAMM2) Common Standard | |
| Compute Express Link (CXL) Memory Module Label | |
| Compute Express Link (CXL\x99) Memory Module Reference Base Standard | |
| Conditions for Measurement of Diode Static Parameters | |
| Conduction Cooled Power Transistors, Thermal Resistance Measurements of | |
| Customer Notification of Product/Process Changes by Semiconductor Suppliers | |
| Customer Notification of Product/Process Changes by Solid-State Suppliers | |
| DDR2 SDRAM SPECIFICATION | |
| DDR3 SDRAM Specification | |
| DDR3 SDRAM Standard | |
| DDR3 SDRAM | |
| DDR4 Data Buffer Defintion (DDR4DB01) | |
| DDR4 NVDIMM-P Bus Protocol | |
| DDR4 Registering Clock Driver - DDR4RCD01 | |
| DDR4 Registering Clock Driver Definition (DDR4RCD02) | |
| DDR4 SDRAM | |
| DDR5 Clock Driver Definition (DDR5CK01) | |
| DDR5 Clock Driver Definition (DDR5CKD01) | |
| DDR5 Clocked Small Outline Dual Inline Memory Module (CSODIMM) Common Specification | |
| DDR5 Clocked Small Outline Dual Inline Memory Module (CSODIMM) Common Standard | |
| DDR5 Clocked Small Outline Dual Inline Memory Module (CSODIMM) Raw Card B Annex | |
| DDR5 Clocked Small Outline Dual Inline Memory Module (CSODIMM) Raw Card C Annex | |
| DDR5 Clocked Small Outline Dual Inline Memory Module with 4-bit ECC (EC4 CSODIMM) Raw Card D Annex | |
| DDR5 Clocked Small Outline Dual Inline Memory Module with 4-bit ECC (EC4 CSODIMM) Raw Card E Annex | |
| DDR5 Clocked Unbuffered Dual Inline Memory Module (CUDIMM) Common Specification | |
| DDR5 Clocked Unbuffered Dual Inline Memory Module (CUDIMM) Common Standard | |
| DDR5 Clocked Unbuffered Dual Inline Memory Module (CUDIMM) Raw Card A Annex | |
| DDR5 Clocked Unbuffered Dual Inline Memory Module (CUDIMM) Raw Card B Annex | |
| DDR5 Clocked Unbuffered Dual Inline Memory Module (CUDIMM) Raw Card C Annex | |
| DDR5 Clocked Unbuffered Dual Inline Memory Module with 4-bit ECC (EC4 CUDIMM) Raw Card D Annex | |
| DDR5 Clocked Unbuffered Dual Inline Memory Module with 4-bit ECC (EC4 CUDIMM) Raw Card E Annex | |
| DDR5 Compression Attached Memory Module (CAMM2) Raw Card A Annex | |
| DDR5 Compression Attached Memory Module (CAMM2) Raw Card C Annex | |
| DDR5 DATA BUFFER DEFINITION (DDR5DB01) | |
| DDR5 DIMM Labels | |
| DDR5 Load Reduced (LRDIMM) and Registered Dual Inline Memory Module (RDIMM) Common Specification | |
| DDR5 RDIMM Standard Annex B | |
| DDR5 RDIMM Standard Annex D | |
| DDR5 Registered Dual Inline Memory Module (RDIMM) Common Standard | |
| DDR5 Registered Dual Inline Memory Module with 8-bit ECC (EC8 RDIMM) Raw Card A Annex | |
| DDR5 Registered Dual Inline Memory Module with 8-bit ECC (EC8 RDIMM) Raw Card C Annex | |
| DDR5 Registered Dual Inline Memory Module with 8-bit ECC (EC8 RDIMM) Raw Card E Annex | |
| DDR5 Registering Clock Driver Definition (DDR5RCD02) | |
| DDR5 Registering Clock Driver Definition (DDR5RCD03) | |
| DDR5 Registering Clock Driver Definition (DDR5RCD04) | |
| DDR5 SDRAM | |
| DDR5 Serial Presence Detect (SPD) Contents | |
| DDR5 Small Outline Dual Inline Memory Module (SODIMM) Common Standard | |
| DDR5 SODIMM Raw Card Annex A | |
| DDR5 SODIMM Raw Card Annex B | |
| DDR5 SODIMM Raw Card Annex C | |
| DDR5 SODIMM Raw Card Annex D | |
| DDR5 SODIMM Raw Card Annex E | |
| DDR5 Unbuffered Dual Inline Memory Module (UDIMM) Common Standard | |
| DDR5 Unbuffered Dual Inline Memory Module (UDIMM) Raw Card A Annex | |
| DDR5 Unbuffered Dual Inline Memory Module (UDIMM) Raw Card B Annex | |
| DDR5 Unbuffered Dual Inline Memory Module (UDIMM) Raw Card C Annex | |
| DDR5 Unbuffered Dual Inline Memory Module with 4-bit ECC (EC4 UDIMM) Raw Card D Annex | |
| DDR5CKD01 Clock Driver | |
| Definition of CDCV857 PLL Clock Driver for Registered DDR DIMM Applications | |
| Definition of CV857 PLL Clock Driver for Registered PC1600, PC2100, and PC2700 DIMM Applications | |
| Definition of CVF857 PLL Clock Driver for Registered PC1600, PC2100, PC2700 a n d PC3200 DIMM Applications | |
| Definition of External Clearance and Creepage Distances of Discrete Semiconductor Packages for Thyristors and Rectifier Diodes | |
| Definition of Skew Specification for Standard Logic Devices | |
| Definition of Skew Specifications for Standard Logic Devices | |
| Definition of the SSTE32882 Registering Clock Driver with Parity and Quad Chip Selects for DDR3 RDIMM Applications | |
| Definition of the SSTE32882 Registering Clock Driver with Parity and Quad Chip Selects for DDR3/DDR3L/DDR3U RDIMM 1.5 V/1.35 V/1.25 V Applications | |
| Definition of the SSTU32864 1.8-V Configurable Registered Buffer for DDR-II RDIMM Applications | |
| Definition of the SSTU32864 1.8-V Configurable Registered Buffer for DDR2 RDIMM Applications | |
| Definition of the SSTU328641.8-V Configurable Registered Buffer for DDR2 RDIMM Applications | |
| Definition of the SSTU32865 28-bit 1:2 Registered Buffer with Parity for DDR2 RDIMM Applications | |
| Definition of the SSTU32865 Registered Buffer with Parity for 2R 4 DDR2 RDIMM Applications | |
| Definition of the SSTU32865 Registered Buffer with Parity for 2R \xd7 4 DDR2 RDIMM Applications | |
| Definition of the SSTU32866 1.8 V Configurable Registered Buffer with Parity Test for DDR2 RDIMM Applications | |
| Definition of the SSTU32866 1.8-V Configurable Registered Buffer with Parity Test for DDR2 RDIMM Applications | |
| Definition of the SSTU32S868 and SSTU32D868 Registered Buffer with Parity for 2R x 4 DDR2 RDIMM Applications | |
| Definition of the SSTU32S869 & SSTU32D869 Registered Buffer with Parity for DDR2 RDIMM Applications | |
| Definition of the SSTU32S869 and SSTU32D869 Registered Buffer with Parity for DDR2 RDIMM Applications | |
| Definition of the SSTUA32866 1.8 V Configurable Registered Buffer with Parity Test for DDR2 RDIMM Applications | |
| Definition of the SSTUA32866 1.8-V Configurable Registered Buffer with Parity Test for DDR2 RDIMM Applications | |
| Definition of the SSTUA32S865 and SSTUA32D865 28-bit 1:2 Registered Buffer with Parity for DDR2 RDIMM Applications | |
| Definition of the SSTUA32S865 DDR2 RDIMM Applications Registered Buffer with Parity for and SSTUA32D865 28-bit 1:2 | |
| Definition of the SSTUA32S868 and SSTUA32D868 Registered Buffer with Parity for 2R x 4 DDR2 RDIMM Applications | |
| Definition of the SSTUA32S869 and SSTUA32D869 DDR2 RDIMM Applications Registered Buffer with Parity for | |
| Definition of the SSTUA32S869 and SSTUA32D869 Registered Buffer with Parity for DDR2 RDIMM Applications | |
| Definition of the SSTUB32865 28-bit 1:2 Registered Buffer with Parity for DDR2 RDIMM Applications | |
| Definition of the SSTUB32865 for DDR2 RDIMM Applications 28-bit 1:2 Registered Buffer with Parity | |
| Definition of the SSTUB32866 1.8 V Configurable Registered Buffer with Parity Test for DDR2 RDIMM Applications | |
| Definition of the SSTUB32868 1.8 V Configurable Registered Buffer with Parity for DDR2 RDIMM Applications | |
| Definition of the SSTUB32868 Registered Buffer with Parity for 2R x 4 DDR2 RDIMM Applications | |
| Definition of the SSTUB32868 Registered Buffer with Parity for 2R x4 DDR2 RDIMM Applications | |
| Definition of the SSTUB32869 Registered Applications Buffer with Parity for DDR2 RDIMM | |
| Definition of the SSTUB32869 Registered Buffer with Parity for DDR2 RDIMM Applications | |
| Definition of the SSTV16857 2.5 V 14-Bit SSTL_2 Registered Buffer for DDR DIMM Applications | |
| Definition of the SSTV16859 2.5 V 13-Bit SSTL_2 Registered Buffer for Stacked DDR DIMM Applications | |
| Definition of the SSTV16859 2.5 V 13-Bit to 26-Bit SSTL_2 Registered Buffer for Stacked DDR DIMM Applications | |
| Definition of the SSTV32852 2.5-V 24-BIT TO 48-Bit SSTL_2 Registered Buffer for 1U Stacked DDR DIMM Applications | |
| Definition of the SSTVN16857 2.5-2.6 V 14-Bit SSTL_2 Registered Buffer for PC1600, PC2100, PC2700, and PC3200 DDR DIMM Applications | |
| Definition of the SSTVN16859 2.5-2.6 V 13-Bit to 26-Bit SSTL_2 Registered Buffer for PC1600, PC2100, PC2700 and PC3200 DDR DIMM Applications | |
| Definition of the SSTVN16859 2.5-2.6 V 13-Bit to 26-Bit SSTL_2 Registered Buffer for PC1600, PC2100, PC2700, and PC3200 DDR DIMM Applications | |
| Description of 1.8 V CMOS Logic Devices | |
| Description of 5 V Bus Switch Devices with TTL-Compatible Control Inputs | |
| Description of a 3.3 V, Zero Delay Clock Distribution Device Compliant with JESD21-C, PC133 Registered DIMM Specification | |
| Description of Low Voltage TTL-Compatible CMOS Logic Devices | |
| Descriptive Designation System for Electronic-device Packages and Footprints | |
| Descriptive Designation System for Electronic-device Packages | |
| Descriptive Designation System for Semiconductor-Device Packages | |
| Designation System for Semiconductor Devices | |
| Desription of a 3.3 V, 18-Bit, LVTTL I/O Register for PC133 Registered DIMM Applications | |
| Device Quality Problem Analysis and Corrective Action Resolution Methodology | |
| DOUBLE DATA RATE (DDR) SDRAM SPECIFICATION | |
| Driver Specifications for 1.8 V Power Supply Point-to-Point Drivers | |
| Early Life Failure Rate Calculation Procedure for Electronic Components | |
| Early Life Failure Rate Calculation Procedure for Semiconductor Components | |
| Electrical Parameters Assessment | |
| Embedded Multi-Media Card (e MMC) Electrical Standard (5.0) | |
| Embedded Multi-Media Card (e MMC) Electrical Standard (5.01) | |
| Embedded Multi-Media Card (e MMC) Electrical Standard (5.1) | |
| Embedded Multi-Media Card (e\x95MMC) Electrical Standard (5.1A) | |
| Embedded Multi-Media Card (e\x95MMC) Electrical Standard (5.1B) | |
| EMBEDDED MULTI-MEDIA CARD (eMMC), ELECTRICAL STANDARD (4.5 Device) | |
| Embedded Multimedia Card (e\x95MMC), Electrical Standard 4.51 | |
| Embedded MultiMediaCard (e\x95MMC) Mechanical Standard, with Optional Reset Signal | |
| Embedded MultiMediaCard (eMMC) eMMC/Card Product Standard, High Capacity, including Reliable Write, Boot, and Sleep Modes (MMCA, 4.3) | |
| Embedded MultiMediaCard (eMMC) Mechanical Standard | |
| Embedded MultiMediaCard (eMMC) Product Standard, High Capacity | |
| Embedded MultiMediaCard (eMMC) Product Standard, Standard Capacity | |
| Embedded MultiMediaCard(e.MMC ) e.MMC/Card Product Standard, High Capacity, including Reliable Write, Boot, Sleep Modes, Dual Data Rate, Multiple Partitions Supports and Security Enhancement (MMCA, 4.4) | |
| Embedded MultiMediaCard(eMMC) eMMC/Card Product Standard, High Capacity, including Reliable Write, Boot, Sleep Modes, Dual Data Rate, Multiple Partitions Supports, Security Enhancement, Background Operation and High Priority Interrupt (MMCA, 4.41) | |
| Extension of Thermal Test Board Standards for Packages with Direct Thermal Attachment Mechanisms | |
| EXTENSION TO JESD51 THERMAL TEST BOARD STANDARDS TO ACCOMMODATE MULTI-CHIP PACKAGES | |
| Failure-Mechanism-Dr iven Reliability Monitoring | |
| FBDIMM Advanced Memory Buffer (AMB) | |
| FBDIMM Specification: High Speed Differential PTP Link at 1.5 V | |
| FBDIMM: Advanced Memory Buffer (AMB) | |
| Fully Buffered DIMM (FBDIMM): DFx Design for Validation and Test | |
| Fully Buffered DIMM Design for Test, Design for Validation (DFx) | |
| General Guidelines for Designing Test Structures for the Wafer-Level Testing of Thin Dielectrics | |
| General Requirements for Authorized Distributors of Commercial and Military Semiconductor Devices | |
| General Requirements for Distributors of Commercial and Military Semiconductor Devices | |
| General Requirements for Distributors of Commercial Semiconductor Devices | |
| Glossary of Thermal Measurement Terms and Definitions | |
| Guidelines for Combining CIE 127-2007 Total Flux Measurements with Thermal Measurements of LEDs with Exposed Cooling Surface | |
| GUIDELINES FOR COMBINING CIE 127:2007 / 225:2017 TOTAL FLUX MEASUREMENTS WITH THERMAL MEASUREMENTS OF LEDS WITH EXPOSED COOLING SURFACE | |
| Guidelines for Reporting and Using Electronic Package Thermal Information | |
| Guidelines for User Notification of Product/Process Changes by Semiconductor Suppliers Errata - 1994 | |
| Guidelines for User Notification of Product/Process Changes by Semiconductor Suppliers | |
| Gunning Transceiver Logic (GTL) Low-Level, High Speed Interface Standard for Digital Integrated Circuits | |
| Gunning Transceiver Logic (GTL) Low-Level, High-Speed Interface Standard for Digital Integrated Circuits | |
| High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages | |
| High Speed Transceiver Logic (HSTL) A 1.5V Output Buffer Supply Voltage Based Interface Standard for Digital Integrated Circuits | |
| HSUL_12 LPDDR2 and LPDDR3 I/O with Optional ODT | |
| HSUL_12 LPDDR2 I/O | |
| Hybrids/MCM | |
| I/O Drivers and Receivers with Configurable Communication Voltage, Impedance, and Receiver Threshold | |
| IC Latch-Up Test | |
| Implementation Of The Electrical Test Method For The Measurement Of Real Thermal Resistance And Impedance Of Light-Emitting Diodes With Exposed Cooling Surface | |
| Implementation of the Electrical Test Method for the Measurement of Real Thermal Resistance and Impedance of Light-Emitting Diodes with Exposed Cooling | |
| Information Requirements for the Qualification of Silicon Devices | |
| Information Requirements for the Qualification of Solid State Devices | |
| Instrumentation Chip Data Sheet for FBDIMM Diagnostic Senselines | |
| Integrated Circuit Thermal Measurement Method - Electrical Test Method (Single Semiconductor Device) | |
| Integrated Circuit Thermal Test Method Environmental Conditions - Forced Convection (Moving Air) | |
| Integrated Circuit Thermal Test Method Environmental Conditions - Junction-to-Board | |
| Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air) | |
| INTERFACE STANDARD FOR 3.3 +/- 0.3 V SUPPLY NONTERMINATED DIGITAL INTEGRATED CIRCUITS | |
| Interface Standard for Nominal 3 V/3.3 V Supply Digital Integrated Circuits | |
| Interoperability and Compliance Technical Requirements for JEDEC Standard JESD96A \x96 Recommended Practice for use with IEEE 802.11n | |
| Isothermal Electromigration Test Procedure | |
| JEDEC Dictionary of Terms for Solid State Technology | |
| JEDEC Dictionary of Terms for Solid-State Technology | |
| JEDEC Memory Controller Standard \x96 for Compute Express Link (CXL) | |
| JEDEC Memory Device Management Standard \x96 for Compute Express Link (CXL) | |
| JEDEC Memory Module Label \x96 for Compute Express Link (CXL) | |
| JEDEC Module Sideband Bus (SidebandBus) | |
| Letter Symbols, Abbreviations, Terms, and Definitions for Discrete Semiconductor and Optoelectronic Devices - Transient Voltage Suppressors | |
| List of Preferred Values for Use on Various Types of Small Signal and Regulator Diodes | |
| LOGNORMAL ANALYSIS OF UNCENSORED DATA AND OF SINGLY RIGHT-CENSORED DATA UTILIZING THE PERSSON AND ROOTZEN METHOD | |
| Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages | |
| Low Power Double Data Rate (LPDDR) SDRAM Specification | |
| Low Power Double Data Rate Interface for Non-Volatile Memory (LPDDR4X-NVM) Standard | |
| LPDDR5/5X Compression Attached Memory Module (CAMM2) Raw Card E Annex | |
| LPDDR5/5X Serial Presence Detect (SPD) Contents | |
| LRDIMM DDR3 Memory Buffer (MB) Version 1.0 | |
| LRDIMM DDR3 Memory Buffer (MB) | |
| Management of Component Obsolescence by Government Contractors | |
| Marking, Symbols, and Labels for Identification of Lead (Pb) Free Assemblies, Components, and Devices | |
| Measurement and Reporting of Alpha Particle and Terrestrial Cosmic Ray-Induced Soft Errors in Semiconductor Devices | |
| Measurement and Reporting of Alpha Particles and Terrestrial Cosmic Ray-Induced Soft Errors in Semiconductor Devices | |
| Measurement Method for Thermal Resistance of Bridge Rectifier Assemblies | |
| Measurement of Small Signal HF, VHF, and UHF Power Gain of Transistors | |
| Measurement of Small Values of Transistor Capacitance | |
| Measurement of Small-Signal VHF-UHF Transistor Short-Circuit Forward Current Transfer Ratio | |
| Measurement of Transistor Noise Figure at MF, HF, and VHF | |
| Mesurement of Temperature Coefficient of Voltage Regulator Diodes | |
| Method for Developing Acceleration Models for Electronic Component Failure Mechanisms | |
| Method for Developing Acceleration Models for Electronic Device Failure Mechanisms | |
| Method of Diode \x93Q\x94 Measurement | |
| Methodology for the Thermal Measurement of Component Packages (Single Semiconductor Device) | |
| Methods for Calculating Failure Rates in Units of FITs | |
| MULTICHIP MODULES (MCM) | |
| MultiMediaCard (MMC) Card Mechanical Standard | |
| MultiMediaCard (MMC) Electrical Standard, High Capacity (MMCA, 4.2) | |
| MultiMediaCard (MMC) Electrical Standard, Standard Capacity (MMCA, 4.1) | |
| N-Channel MOSFET Hot Carrier Data Analysis | |
| Numbering of Like-Named Terminal Functions in Semiconductor Devices and Designation of Units in Multiple-Unit Semiconductor Devices | |
| Outlier Identification and Management System for Electronic Components | |
| Overview of Methodologies for the Thermal Measurement of Single- and Multi-Chip, Single- and Multi-PN-Junction Light-Emitting Diodes (LEDs) | |
| PMIC5000/PMIC5010 Power Management IC Standard | |
| PMIC5020 Power Management IC Standard | |
| PMIC50x0 Power Management IC Standard | |
| PMIC5100 Power Management IC Standard | |
| PMIC5120 Power Management IC Standard | |
| PMIC5200 Power Management IC Standard | |
| POD10 - 1.0 V PSEUDO OPEN DRAIN INTERFACE | |
| POD12 - 1.2 V PSEUDO OPEN DRAIN INTERFACE | |
| POD125 - 1.25 V Pseudo Open Drain I/O | |
| POD135 - 1.35 V Pseudo Open Drain I/O | |
| POD15 - 1.5 V Pseudo Open Drain I/O | |
| POD18 - 1.8 V Pseudo Open Drain I/O | |
| Procedure for Characterizing Time- Dependent Dielectric Breakdown of Ultra-Thin Gate Dielectrics | |
| Procedure for Measuring N-Channel MOSFET Hot-Carrier-Induced Degradation under DC Stress | |
| Procedure for Measuring P-Channel MOSFET Hot-Carrier-Induced Degradation at Maximum Gate Current under DC Stress | |
| Procedure for the Wafer-Level Testing of Thin Dielectrics | |
| Procurement Standard for Known Good Die (KGD) | |
| Procurement Standard for Semiconductor Die Products Including Known Good Die (KGD) | |
| Product Discontinuance | |
| PSO-N/PQFN Pinouts Standardized for 14-, 16-, 20-, and 24-Lead Logic Functions | |
| QUALITY SYSTEM ASSESSMENT | |
| Radio Front End-Baseband (RF-BB) Interface | |
| Ranges and Conditions for Specifying Beta for Low Power, Audio Frequency Transistors for Entertainment Service | |
| Requirements for Handling Electrostatic-Discha rge-Sensitive (ESDS) Devices | |
| Reverse Recovery Characteristics of Silicon Diodes | |
| Scalable Low-Voltage Signalling for 400 mV (SLVS-400) | |
| Silicon Rectifier Diodes | |
| SON/QFN Package Pinouts Standardized for 1-, 2-, and 3-Bit Logic Functions | |
| SPD5118 Hub and Serial Presence Detect Device Standard | |
| SPD5118, SPD5108 Hub and Serial Presence Detect Device Standard | |
| Special Requirements for Maverick Product Elimination and Outlier Management | |
| Special Requirements for Maverick Product Elimination | |
| Standard Data Transfer Format Between Data Preparation System and Programmable Logic Device Programmer | |
| Standard Description of 1.2 V CMOS Logic Devices (Normal Range Operations) | |
| Standard Description of 1.2 V CMOS Logic Devices (Wide Range Operations) | |
| Standard Description of 1.5 V CMOS Logic Devices | |
| Standard for China Description File | |
| Standard for Definition of CU877 PLL Clock Driver for Registered DDR2 DIMM Applications | |
| Standard for Definition of CU878 PLL Clock Driver for Registered DDR2 DIMM Applications | |
| Standard for Definition of CUA845 PLL Clock Driver for Registered DDR2 DIMM Applications | |
| Standard for Definition of CUA877 and CU2A877 PLL Clock Drivers for for Registered DDR2 DIMM Applications | |
| Standard for Definition of CUA877 PLL Clock Driver for Registered DDR2 DIMM Applications | |
| Standard for Definition of CUA878 PLL Clock Driver for Registered DDR2 DIMM Applications | |
| Standard for Description of 2.5 V CMOS Logic Devices with 3.6 V CMOS Tolerant Inputs and Outputs | |
| Standard for Description of 2.5 V CMOS Logic Devices | |
| Standard for Description of 3.3 V NFET Bus Switch Devices with Integrated Charge Pumps | |
| Standard for Description of 3.3 V NFET Bus Switch Devices | |
| Standard for Description of 3867: 2.5 V, 10-Bit, 2-Port, DDR FET Switch | |
| Standard for Description of 54/74ABTXXX and 74BCXXX TTL-Compatibility BiCMOS Logic Devices | |
| Standard for Description of Low-Voltage TTL-Compatible BiCMOS Logic Devices | |
| Standard for Description of Low-Voltage TTL-Compatible, 5 V-Tolerant CMOS Logic Devices | |
| Standard for Failure Analysis Report Format | |
| Standard for Lognormal Analysis of Uncensored Data, and of Singly Right-Censored Data Utilizing the Persson and Rootzen Method | |
| Standard for Measuring Forward Switching Characteristics of Semiconductor Diodes | |
| Standard for Operating Voltages and Interface Levels for Low Voltage Emitter-Coupled Logic (ECL) Integrated Circuits | |
| Standard for the Measurement of CRE | |
| Standard for the Measurement of Small-Signal Transistor Scattering Parameters | |
| Standard List of Values to be Used in Semiconductor Device Specifications and Registration Formats | |
| Standard Method for Calculating the Electromigration Model Parameters for Current Density and Temperature | |
| Standard Method for Measuring and Using the Temperature Coefficient of Resistance to Determine the Temperature of a Metallization Line | |
| Standard Test and Programming Language (STAPL) | |
| Standard Test Procedure for Noise Margin Measurements for Semiconductor Logic Gating Microcircuits | |
| Standard Test Structures for Reliability Assessment of AICu Metallizations with Barrier Materials | |
| Statistical Process Control Systems | |
| Stress-Test-Driven Qualification of Integrated Circuits | |
| Stub Series Terminated Logic for 1.8 V (SSTL_18) | |
| Stub Series Terminated Logic for 2.5 Volts (SSTL_2) | |
| Stub Series Terminated Logic for 3.3 Volts (SSTL-3) | |
| Symbol and Label for Electrostatic Sensitive Devices | |
| System Soft Error Rate (SSER) Test Method | |
| Temperature Range and Measurement Standards for Components and Modules | |
| Terms, Definitions and Units Glossary for LED Thermal Testing | |
| Terms, Definitions, and Letter Symbols for Discrete Semiconductor and Optoelectronic Devices | |
| Terms, Definitions, and Letter Symbols for Microelectronic Devices | |
| Test Boards for Area Array Surface Mount Package Thermal Measurements | |
| Test Boards for Through-Hole Area Array Leaded Package Thermal Measurements | |
| Test Boards for Through-Hole Perimeter Leaded Package Thermal Measurements | |
| Test Criteria for the Wafer-Level Testing of Thin Dielectrics | |
| Test Method For Alpha Source Accelerated Soft Error Rate | |
| Test Method for Beam Accelerated Soft Error Rate | |
| Test Method for Real-Time Soft Error Rate | |
| Test Methods and Acceptance Procedures for the Evaluation of Polymeric Materials | |
| Test Methods for the Collector-Base Time Constant and for the Resistive Part of the Common-Emitter Input Impedance | |
| Test Procedures for the Measurement of Single-Event Effects in Semiconductor Devices from Heavy Ion Irradiation | |
| The Measurement of Small-Signal VHF-UHF Transistor Admittance Parameters | |
| The Measurement of Transistor Equivalent Noise Voltage and Equivalent Noise Current at Frequencies of up to 20 kHz | |
| The Measurement of Transistor Noise Figure at Frequencies up to 20 kHz by Sinusoidal Signal-Generator Method | |
| Thermal Resistance Test Method for Signal and Regulator Diodes (Forward Voltage, Switching Method) | |
| THERMAL TEST CHIP GUIDELINE (WIRE BOND AND FLIP CHIP) | |
| Thermal Test Chip Guideline (Wire Bond Type Chip) | |
| Thermal Test Environment Modifications for MultiChip Packages | |
| Transient Dual Interface Test Method for the Measurement of the Thermal Resistance Junction to Case of Semiconductor Devices with Heat Flow Trough a Single Path | |
| Transient Voltage Suppressor Standard for Thyristor Surge Protective Device Rating Verification and Characteristic Testing | |
| TS5111, TS5110 Serial Bus Thermal Sensor Device Standard | |
| TS511X, TS521X Serial Bus Thermal Sensor Device Standard | |
| Unified Wide Power Supply Voltage Range CMOS DC Interface Standard for Non-Terminated Digital Integrated Circuits | |
| Voltage Regulator Diode Noise Voltage Measurement |
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