Nexperia B.V. Dual D-type flip-flop with set and reset; positive-edge trigger 74ALVC74D,118

The 74ALVC74 is a dual positive edge triggered D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs, and complementary Q and Qoutputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the Q output.

Schmitt trigger action on all inputs makes the device tolerant of slow rise and fall times.

This device is fully specified for partial power down applications using I_OFF. The I_OFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

Features and benefits

• Wide supply voltage range from 1.65 V to 3.6 V
• CMOS low power dissipation
• Overvoltage tolerant inputs to 3.6 V
• Direct interface with TTL levels
• I_OFF circuitry provides partial Power-down mode operation
• Latch-up performance exceeds 250 mA per JESD78 Class II.A
• Complies with JEDEC standard:
• JESD8-7 (1.65 to 1.95 V)
• JESD8-5 (2.3 to 2.7 V)
• JESD8C/JESD36 (2.7 V to 3.6 V)
• ESD protection:
• HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
• CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
• Specified from -40 °C to +85 °C and from -40 °C to +125 °C

IC FF D-TYPE DOUBLE 1-BIT 14-SO

IC FF D-TYPE DOUBLE 1-BIT 14-SO

"Flip Flop 2 Element D-Type 1 Bit Positive Edge 14-SOIC (0.154"", 3.90mm Width)"

D Flip-Flop, ALVC/VCX/A Series, 2-Func, Positive Edge Triggered, 1-Bit, Complementary Output, CMOS, PDSO14