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Nexperia B.V. 18-bit bus-interface D-type flip-flop with reset and enable with 30 Ohm termination resistors; 3-state 74ALVT162823DGG,11

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18-bit bus-interface D-type flip-flop with reset and enable with 30 Ohm termination resistors; 3-state - 74ALVT162823DGG,11 - Nexperia B.V.
Nijmegen, Netherlands
18-bit bus-interface D-type flip-flop with reset and enable with 30 Ohm termination resistors; 3-state
74ALVT162823DGG,11
18-bit bus-interface D-type flip-flop with reset and enable with 30 Ohm termination resistors; 3-state 74ALVT162823DGG,11
The 74ALVT162823 18-bit bus interface register is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data or address paths of buses carrying parity. The 74ALVT162823 has two 9-bit wide buffered registers with clock enable (nCE) and master reset (nMR) which are ideal for parity bus interfacing in high microprogrammed systems. The registers are fully edge-triggered. The state of each D input, one set-up time before the LOW-to-HIGH clock transition is transferred to the corresponding Q output of the flip-flop. The 74ALVT162823 is designed with 30 Ω series resistance in both the pull-up and pull-down output structures. This design reduces line noise in applications such as memory address drivers, clock drivers, and bus receivers or transmitters. Features and benefits Two sets of high speed parallel registers with positive edge-triggered D-type flip-flops 5 V I/O compatible Ideal where high speed, light loading or increased fan-in are required with MOS microprocessors Bus hold data inputs eliminate the need for external pull-up resistors to hold unused inputs Live insertion and extraction permitted Power-up 3-state Power-up reset Output capability: +12 mA to -12 mA Outputs include series resistance of 30 Ω making external termination resistors unnecessary Latch-up protection: JESD78: exceeds 500 mA ESD protection: MIL STD 883, method 3015: exceeds 2000 V Machine Model: exceeds 200 V

The 74ALVT162823 18-bit bus interface register is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data or address paths of buses carrying parity.

The 74ALVT162823 has two 9-bit wide buffered registers with clock enable (nCE) and master reset (nMR) which are ideal for parity bus interfacing in high microprogrammed systems.

The registers are fully edge-triggered. The state of each D input, one set-up time before the LOW-to-HIGH clock transition is transferred to the corresponding Q output of the flip-flop.

The 74ALVT162823 is designed with 30 Ω series resistance in both the pull-up and pull-down output structures. This design reduces line noise in applications such as memory address drivers, clock drivers, and bus receivers or transmitters.

Features and benefits

  • Two sets of high speed parallel registers with positive edge-triggered D-type flip-flops
  • 5 V I/O compatible
  • Ideal where high speed, light loading or increased fan-in are required with MOS microprocessors
  • Bus hold data inputs eliminate the need for external pull-up resistors to hold unused inputs
  • Live insertion and extraction permitted
  • Power-up 3-state
  • Power-up reset
  • Output capability: +12 mA to -12 mA
  • Outputs include series resistance of 30 Ω making external termination resistors unnecessary
  • Latch-up protection:
    • JESD78: exceeds 500 mA
  • ESD protection:
    • MIL STD 883, method 3015: exceeds 2000 V
    • Machine Model: exceeds 200 V
Supplier's Site Datasheet
Logic - Flip Flops - 74ALVT162823DGG,11 - Lingto Electronic Limited
Shenzhen, China
Logic - Flip Flops
74ALVT162823DGG,11
Logic - Flip Flops 74ALVT162823DGG,11
IC FF D-TYPE DUAL 9BIT 56TSSOP

IC FF D-TYPE DUAL 9BIT 56TSSOP

Supplier's Site Datasheet
Flip Flops - 74ALVT162823DGG,11 - Quarktwin Technology Ltd.
Shenzhen, Guangdong, China
Flip Flop 2 Element D-Type 9 Bit Positive Edge 56-TFSOP (0.240", 6.10mm Width)

Flip Flop 2 Element D-Type 9 Bit Positive Edge 56-TFSOP (0.240", 6.10mm Width)

Supplier's Site Datasheet

Technical Specifications

  Nexperia B.V. Lingto Electronic Limited Quarktwin Technology Ltd.
Product Category Flip-Flops Flip-Flops Flip-Flops
Product Number 74ALVT162823DGG,11 74ALVT162823DGG,11 74ALVT162823DGG,11
Product Name 18-bit bus-interface D-type flip-flop with reset and enable with 30 Ohm termination resistors; 3-state Logic - Flip Flops Flip Flops
Flip-Flop Type D D
Supply Voltage 2.5V; 3V; 3.3V; 3.6V; 2.3 - 3.6 3V; 3.6V; 2.3V ~ 2.7V, 3V ~ 3.6V
Output Characteristics 3-State; OE
Features ESD Protection
Propagation Delay 3 ns
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