TP5335 is a P-channel enhancement-mode vertical DMOS FET in a 3-lead SOT-23 package, measuring 2.90 mm × 1.30 mm with a maximum height of 1.12 mm. It has a drain-to-source breakdown voltage of -350 V, a gate-source threshold voltage ranging from -1 V to -2.4 V, and a static drain-to-source on-state resistance of 30 Ω at -10 V gate bias. The device supports a maximum junction temperature of 150°C and a thermal resistance of 203 °C/W. It features an integral source-drain diode, is free from thermal runaway and secondary breakdown, and meets RoHS requirements. Automotive-grade versions are available with 100% testing at -55°C, 25°C, and 150°C.
TP5335 is a low threshold enhancement-mode (normally-off) transistor utilizing an advanced vertical DMOS structure and well-proven silicon-gate manufacturing process. This combination produces a device with the power handling capabilities of bipolar transistors and with the high input impedance and positive temperature coefficient inherent in MOS devices. Characteristic of all MOS structures, this device is free from thermal runaway and thermally-induced secondary breakdown. Vertical DMOS FETs are ideally suited to a wide range of switching and amplifying applications where high breakdown voltage, high input impedance, low input capacitance, and fast switching speeds are desired.
Additional Features
| Microchip Technology, Inc. | |
|---|---|
| Product Category | Metal-Oxide Semiconductor FET (MOSFET) |
| Product Number | TP5335 |
| Product Name | P-Channel Enhancement Mode MOSFET |
| Polarity | P-Channel |
