Microchip Technology, Inc. 10/100 Base-T/TX Ethernet Controller with 16 Bit Interface LAN9221

Description
The LAN9221/LAN9221i is a full-featured, single-chip 10/100 Ethernet controller designed for embedded applications where performance, flexibility, ease of integration and system cost control are required. The LAN9221/LAN9221i has been specifically designed to provide high performance and throughput for 16-bit applications. The LAN9221/LAN9221i is fully IEEE 802.3 10BASE-T and 802.3u 100BASE-TX compliant, and supports HP Auto-MDIX. The variable voltage I/O signals of the LAN9221/LAN9221i accommodate lower voltage I/O signalling without the need for voltage level shifters. The LAN9221/LAN9221i includes an integrated Ethernet MAC and PHY with a high-performance SRAM-like slave interface. The simple, yet highly functional host bus interface provides a glue-less connection to most common 16-bit microprocessors and microcontrollers as well as 32-bit microprocessors with a 16-bit external bus. The integrated checksum offload engines enable the automatic generation of the 16-bit checksum for received and transmitted Ethernet frames, offloading the task from the CPU. The LAN9221/LAN9221i also includes large transmit and receive data FIFOs to accommodate high latency applications. In addition, the LAN9221/LAN9221i memory buffer architecture allows highly efficient use of memory resources by optimizing packet granularity. The 93AA46AE48 EEPROM device from Microchip comes with a factory programmed, globally unique EUI-48™ MAC Address. This Ethernet controller will automatically detect and load the EUI-48™ node address from the 93AA46AE48 EEPROM at start-up or reset. *The LANCheck online design review service is subject to Microchip's Program Terms and Conditions and requires a myMicrochip account. Additional Features Highlights Optimized for high performance applications Efficient architecture with low CPU overhead Easily interfaces to most 16-bit embedded CPU's 1.8V to 3.3V variable voltage I/O accommodates wide range of I/O signaling without voltage level shifters Integrated PHY with HP Auto-MDIX support Integrated checksum offload engine helps reduce CPU load Low pin count and small body size package for small form factor system designs Target Applications Cable, satellite, and IP set-top boxes Digital video recorders and DVD recorder/players Digital TV Digital media clients/servers and home gateways Video-over IP solutions, IP PBX & video phones Wireless routers & access points High-end audio distribution systems Key Benefits Non-PCI Ethernet controller for high performance applications 16-bit interface with fast bus cycle times Burst-mode read support Minimizes dropped packets Internal buffer memory can store over 200 packets Automatic PAUSE and back-pressure flow control Minimizes CPU overhead Supports Slave-DMA Interrupt Pin with Programmable Hold-off timer Reduces system cost and increases design flexibility SRAM-like interface easily interfaces to most Embedded CPU's or SoC's Reduced-Power Modes Numerous power management modes Wake on LAN Magic packet wakeup Wakeup indicator event signal Link Status Change Single chip Ethernet controller Fully compliant with IEEE 802.3/802.3u standards Integrated Ethernet MAC and PHY 10BASE-T and 100BASE-TX support Full- and Half-duplex support Full-duplex flow control Backpressure for half-duplex flow control Preamble generation and removal Automatic 32-bit CRC generation and checking Automatic payload padding and pad removal Loop-back modes Flexible address filtering modes One 48-bit perfect address 64 hash-filtered multicast addresses Pass all multicast Promiscuous mode Inverse filtering Pass all incoming with status report Disable reception of broadcast packets Integrated 10/100 Ethernet PHY Supports HP Auto-MDIX Auto-negotiation Supports energy-detect power down Host bus interface Simple, SRAM-like interface 16-bit data bus 16Kbyte FIFO with flexible TX/RX allocation One configurable host interrupt Miscellaneous features Small form factor, 56-pin QFN RoHS Compliant package Integrated 1.8V regulator Integrated checksum offload engine Mixed endian support General Purpose Timer Optional EEPROM interface Support for 3 status LEDs multiplexed with Programmable GPIO signals Single 3.3V Power Supply with Variable Voltage I/O Commercial and Industrial Temperature Support
Datasheet
Description
The LAN9221/LAN9221i is a full-featured, single-chip 10/100 Ethernet controller designed for embedded applications where performance, flexibility, ease of integration and system cost control are required. The LAN9221/LAN9221i has been specifically designed to provide high performance and throughput for 16-bit applications. The LAN9221/LAN9221i is fully IEEE 802.3 10BASE-T and 802.3u 100BASE-TX compliant, and supports HP Auto-MDIX. The variable voltage I/O signals of the LAN9221/LAN9221i accommodate lower voltage I/O signalling without the need for voltage level shifters. The LAN9221/LAN9221i includes an integrated Ethernet MAC and PHY with a high-performance SRAM-like slave interface. The simple, yet highly functional host bus interface provides a glue-less connection to most common 16-bit microprocessors and microcontrollers as well as 32-bit microprocessors with a 16-bit external bus. The integrated checksum offload engines enable the automatic generation of the 16-bit checksum for received and transmitted Ethernet frames, offloading the task from the CPU. The LAN9221/LAN9221i also includes large transmit and receive data FIFOs to accommodate high latency applications. In addition, the LAN9221/LAN9221i memory buffer architecture allows highly efficient use of memory resources by optimizing packet granularity. The 93AA46AE48 EEPROM device from Microchip comes with a factory programmed, globally unique EUI-48™ MAC Address. This Ethernet controller will automatically detect and load the EUI-48™ node address from the 93AA46AE48 EEPROM at start-up or reset. *The LANCheck online design review service is subject to Microchip's Program Terms and Conditions and requires a myMicrochip account. Additional Features Highlights Optimized for high performance applications Efficient architecture with low CPU overhead Easily interfaces to most 16-bit embedded CPU's 1.8V to 3.3V variable voltage I/O accommodates wide range of I/O signaling without voltage level shifters Integrated PHY with HP Auto-MDIX support Integrated checksum offload engine helps reduce CPU load Low pin count and small body size package for small form factor system designs Target Applications Cable, satellite, and IP set-top boxes Digital video recorders and DVD recorder/players Digital TV Digital media clients/servers and home gateways Video-over IP solutions, IP PBX & video phones Wireless routers & access points High-end audio distribution systems Key Benefits Non-PCI Ethernet controller for high performance applications 16-bit interface with fast bus cycle times Burst-mode read support Minimizes dropped packets Internal buffer memory can store over 200 packets Automatic PAUSE and back-pressure flow control Minimizes CPU overhead Supports Slave-DMA Interrupt Pin with Programmable Hold-off timer Reduces system cost and increases design flexibility SRAM-like interface easily interfaces to most Embedded CPU's or SoC's Reduced-Power Modes Numerous power management modes Wake on LAN Magic packet wakeup Wakeup indicator event signal Link Status Change Single chip Ethernet controller Fully compliant with IEEE 802.3/802.3u standards Integrated Ethernet MAC and PHY 10BASE-T and 100BASE-TX support Full- and Half-duplex support Full-duplex flow control Backpressure for half-duplex flow control Preamble generation and removal Automatic 32-bit CRC generation and checking Automatic payload padding and pad removal Loop-back modes Flexible address filtering modes One 48-bit perfect address 64 hash-filtered multicast addresses Pass all multicast Promiscuous mode Inverse filtering Pass all incoming with status report Disable reception of broadcast packets Integrated 10/100 Ethernet PHY Supports HP Auto-MDIX Auto-negotiation Supports energy-detect power down Host bus interface Simple, SRAM-like interface 16-bit data bus 16Kbyte FIFO with flexible TX/RX allocation One configurable host interrupt Miscellaneous features Small form factor, 56-pin QFN RoHS Compliant package Integrated 1.8V regulator Integrated checksum offload engine Mixed endian support General Purpose Timer Optional EEPROM interface Support for 3 status LEDs multiplexed with Programmable GPIO signals Single 3.3V Power Supply with Variable Voltage I/O Commercial and Industrial Temperature Support
Datasheet

Suppliers

Company
Product
Description
Supplier Links
10/100 Base-T/TX Ethernet Controller with 16 Bit Interface - LAN9221 - Microchip Technology, Inc.
Chandler, AZ, United States
10/100 Base-T/TX Ethernet Controller with 16 Bit Interface
LAN9221
10/100 Base-T/TX Ethernet Controller with 16 Bit Interface LAN9221
The LAN9221/LAN9221i is a full-featured, single-chip 10/100 Ethernet controller designed for embedded applications where performance, flexibility, ease of integration and system cost control are required. The LAN9221/LAN9221i has been specifically designed to provide high performance and throughput for 16-bit applications. The LAN9221/LAN9221i is fully IEEE 802.3 10BASE-T and 802.3u 100BASE-TX compliant, and supports HP Auto-MDIX. The variable voltage I/O signals of the LAN9221/LAN9221i accommodate lower voltage I/O signalling without the need for voltage level shifters. The LAN9221/LAN9221i includes an integrated Ethernet MAC and PHY with a high-performance SRAM-like slave interface. The simple, yet highly functional host bus interface provides a glue-less connection to most common 16-bit microprocessors and microcontrollers as well as 32-bit microprocessors with a 16-bit external bus. The integrated checksum offload engines enable the automatic generation of the 16-bit checksum for received and transmitted Ethernet frames, offloading the task from the CPU. The LAN9221/LAN9221i also includes large transmit and receive data FIFOs to accommodate high latency applications. In addition, the LAN9221/LAN9221i memory buffer architecture allows highly efficient use of memory resources by optimizing packet granularity. The 93AA46AE48 EEPROM device from Microchip comes with a factory programmed, globally unique EUI-48™ MAC Address. This Ethernet controller will automatically detect and load the EUI-48™ node address from the 93AA46AE48 EEPROM at start-up or reset. *The LANCheck online design review service is subject to Microchip's Program Terms and Conditions and requires a myMicrochip account. Additional Features Highlights Optimized for high performance applications Efficient architecture with low CPU overhead Easily interfaces to most 16-bit embedded CPU's 1.8V to 3.3V variable voltage I/O accommodates wide range of I/O signaling without voltage level shifters Integrated PHY with HP Auto-MDIX support Integrated checksum offload engine helps reduce CPU load Low pin count and small body size package for small form factor system designs Target Applications Cable, satellite, and IP set-top boxes Digital video recorders and DVD recorder/players Digital TV Digital media clients/servers and home gateways Video-over IP solutions, IP PBX & video phones Wireless routers & access points High-end audio distribution systems Key Benefits Non-PCI Ethernet controller for high performance applications 16-bit interface with fast bus cycle times Burst-mode read support Minimizes dropped packets Internal buffer memory can store over 200 packets Automatic PAUSE and back-pressure flow control Minimizes CPU overhead Supports Slave-DMA Interrupt Pin with Programmable Hold-off timer Reduces system cost and increases design flexibility SRAM-like interface easily interfaces to most Embedded CPU's or SoC's Reduced-Power Modes Numerous power management modes Wake on LAN Magic packet wakeup Wakeup indicator event signal Link Status Change Single chip Ethernet controller Fully compliant with IEEE 802.3/802.3u standards Integrated Ethernet MAC and PHY 10BASE-T and 100BASE-TX support Full- and Half-duplex support Full-duplex flow control Backpressure for half-duplex flow control Preamble generation and removal Automatic 32-bit CRC generation and checking Automatic payload padding and pad removal Loop-back modes Flexible address filtering modes One 48-bit perfect address 64 hash-filtered multicast addresses Pass all multicast Promiscuous mode Inverse filtering Pass all incoming with status report Disable reception of broadcast packets Integrated 10/100 Ethernet PHY Supports HP Auto-MDIX Auto-negotiation Supports energy-detect power down Host bus interface Simple, SRAM-like interface 16-bit data bus 16Kbyte FIFO with flexible TX/RX allocation One configurable host interrupt Miscellaneous features Small form factor, 56-pin QFN RoHS Compliant package Integrated 1.8V regulator Integrated checksum offload engine Mixed endian support General Purpose Timer Optional EEPROM interface Support for 3 status LEDs multiplexed with Programmable GPIO signals Single 3.3V Power Supply with Variable Voltage I/O Commercial and Industrial Temperature Support

The LAN9221/LAN9221i is a full-featured, single-chip 10/100 Ethernet controller designed for embedded applications where performance, flexibility, ease of integration and system cost control are required. The LAN9221/LAN9221i has been specifically designed to provide high performance and throughput for 16-bit applications. The LAN9221/LAN9221i is fully IEEE 802.3 10BASE-T and 802.3u 100BASE-TX compliant, and supports HP Auto-MDIX. The variable voltage I/O signals of the LAN9221/LAN9221i accommodate lower voltage I/O signalling without the need for voltage level shifters.

The LAN9221/LAN9221i includes an integrated Ethernet MAC and PHY with a high-performance SRAM-like slave interface. The simple, yet highly functional host bus interface provides a glue-less connection to most common 16-bit microprocessors and microcontrollers as well as 32-bit microprocessors with a 16-bit external bus. The integrated checksum offload engines enable the automatic generation of the 16-bit checksum for received and transmitted Ethernet frames, offloading the task from the CPU. The LAN9221/LAN9221i also includes large transmit and receive data FIFOs to accommodate high latency applications. In addition, the LAN9221/LAN9221i memory buffer architecture allows highly efficient use of memory resources by optimizing packet granularity.
The 93AA46AE48 EEPROM device from Microchip comes with a factory programmed, globally unique EUI-48™ MAC Address. This Ethernet controller will automatically detect and load the EUI-48™ node address from the 93AA46AE48 EEPROM at start-up or reset.


*The LANCheck online design review service is subject to Microchip's Program Terms and Conditions and requires a myMicrochip account. Additional Features

    Highlights
    • Optimized for high performance applications
    • Efficient architecture with low CPU overhead
    • Easily interfaces to most 16-bit embedded CPU's
    • 1.8V to 3.3V variable voltage I/O accommodates wide range of I/O signaling without voltage level shifters
    • Integrated PHY with HP Auto-MDIX support
    • Integrated checksum offload engine helps reduce CPU load
    • Low pin count and small body size package for small form factor system designs
    Target Applications
    • Cable, satellite, and IP set-top boxes
    • Digital video recorders and DVD recorder/players
    • Digital TV
    • Digital media clients/servers and home gateways
    • Video-over IP solutions, IP PBX & video phones
    • Wireless routers & access points
    • High-end audio distribution systems
    Key Benefits
    • Non-PCI Ethernet controller for high performance applications
      • 16-bit interface with fast bus cycle times
      • Burst-mode read support
    • Minimizes dropped packets
      • Internal buffer memory can store over 200 packets
      • Automatic PAUSE and back-pressure flow control
    • Minimizes CPU overhead
      • Supports Slave-DMA
      • Interrupt Pin with Programmable Hold-off timer
    • Reduces system cost and increases design flexibility
    • SRAM-like interface easily interfaces to most Embedded CPU's or SoC's
    • Reduced-Power Modes
      • Numerous power management modes
      • Wake on LAN
      • Magic packet wakeup
      • Wakeup indicator event signal
      • Link Status Change
    • Single chip Ethernet controller
      • Fully compliant with IEEE 802.3/802.3u standards
      • Integrated Ethernet MAC and PHY
      • 10BASE-T and 100BASE-TX support
      • Full- and Half-duplex support
      • Full-duplex flow control
      • Backpressure for half-duplex flow control
      • Preamble generation and removal
      • Automatic 32-bit CRC generation and checking
      • Automatic payload padding and pad removal
      • Loop-back modes
    • Flexible address filtering modes
      • One 48-bit perfect address
      • 64 hash-filtered multicast addresses
      • Pass all multicast
      • Promiscuous mode
      • Inverse filtering
      • Pass all incoming with status report
      • Disable reception of broadcast packets
    • Integrated 10/100 Ethernet PHY
      • Supports HP Auto-MDIX
      • Auto-negotiation
      • Supports energy-detect power down
    • Host bus interface
      • Simple, SRAM-like interface
      • 16-bit data bus
      • 16Kbyte FIFO with flexible TX/RX allocation
      • One configurable host interrupt
    • Miscellaneous features
      • Small form factor, 56-pin QFN RoHS Compliant package
      • Integrated 1.8V regulator
      • Integrated checksum offload engine
      • Mixed endian support
      • General Purpose Timer
      • Optional EEPROM interface
      • Support for 3 status LEDs multiplexed with Programmable GPIO signals
    • Single 3.3V Power Supply with Variable Voltage I/O
    • Commercial and Industrial Temperature Support
Supplier's Site Datasheet

Technical Specifications

  Microchip Technology, Inc.
Product Category Network Cards and Network Controllers
Product Number LAN9221
Product Name 10/100 Base-T/TX Ethernet Controller with 16 Bit Interface
Host Bus 16 bit Host Bus
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