Integrated Device Technology Low Skew,1-to-4 Differential/LVCMOS-to-0.7V HCSL Fanout Buffer 85104AGILFT

Description
The 85104I is a low skew, high performance 1-to-4 Differential/ LVCMOS -to-0.7V HCSL Fanout Buffer. The 85104I has two selectable clock inputs. The CLK0 , nCLK0 pair can accept most standard differential input levels. The single-ended CLK1 can accept LVCMOS or LVTTL input levels. The clock enable is internally synchronized to eliminate runt clock pulses on the outputs during asynchronous assertion/deassertio n of the clock enable pin. Guaranteed output and part-to-part skew characteristics make the 85104I ideal for those applications demanding well defined performance and repeatability.
Datasheet
Description
The 85104I is a low skew, high performance 1-to-4 Differential/ LVCMOS -to-0.7V HCSL Fanout Buffer. The 85104I has two selectable clock inputs. The CLK0 , nCLK0 pair can accept most standard differential input levels. The single-ended CLK1 can accept LVCMOS or LVTTL input levels. The clock enable is internally synchronized to eliminate runt clock pulses on the outputs during asynchronous assertion/deassertio n of the clock enable pin. Guaranteed output and part-to-part skew characteristics make the 85104I ideal for those applications demanding well defined performance and repeatability.
Datasheet

Suppliers

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Low Skew,1-to-4 Differential/LVCMOS-to-0.7V HCSL Fanout Buffer - 85104AGILFT - Integrated Device Technology
San Jose, CA, USA
Low Skew,1-to-4 Differential/LVCMOS-to-0.7V HCSL Fanout Buffer
85104AGILFT
Low Skew,1-to-4 Differential/LVCMOS-to-0.7V HCSL Fanout Buffer 85104AGILFT
The 85104I is a low skew, high performance 1-to-4 Differential/ LVCMOS -to-0.7V HCSL Fanout Buffer. The 85104I has two selectable clock inputs. The CLK0 , nCLK0 pair can accept most standard differential input levels. The single-ended CLK1 can accept LVCMOS or LVTTL input levels. The clock enable is internally synchronized to eliminate runt clock pulses on the outputs during asynchronous assertion/deassertio n of the clock enable pin. Guaranteed output and part-to-part skew characteristics make the 85104I ideal for those applications demanding well defined performance and repeatability.

The 85104I is a low skew, high performance 1-to-4 Differential/ LVCMOS -to-0.7V HCSL Fanout Buffer. The 85104I has two selectable clock inputs. The CLK0 , nCLK0 pair can accept most standard differential input levels. The single-ended CLK1 can accept LVCMOS or LVTTL input levels. The clock enable is internally synchronized to eliminate runt clock pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. Guaranteed output and part-to-part skew characteristics make the 85104I ideal for those applications demanding well defined performance and repeatability.

Supplier's Site Datasheet

Technical Specifications

  Integrated Device Technology
Product Category IC Interfaces
Product Number 85104AGILFT
Product Name Low Skew,1-to-4 Differential/LVCMOS-to-0.7V HCSL Fanout Buffer
Technology CMOS
Device Type Buffer
Supply Voltage 3.3V
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