Integrated Device Technology Dual VCXO W/3.3V,2.5V LVPECL FemtoClock PLL 813001AGILFT

Description
The 813001I is a dual VCXO + FemtoClock® Multiplier designed for use in Discrete PLL loops. Two selectable external VCXO crystals allow the device to be used in multi-rate applications, where a given line card can be switched, for example, between 1Gb Ethernet (125MHz system reference clock) and 1Gb Fibre Channel (106.25MHz system reference clock) modes. Of course, a multitude of other applications are also possible such as switching between 74.25MHz and 74.175824MHz for HDTV , switching between SONET , FEC and non FEC rates, etc. The 813001I is a two stage device – a VCXO followed by a FemtoClock PLL . The FemtoClock PLL can multiply the crystal frequency of the VCXO to provide an output frequency range of 40.83MHz to 640MHz, with a random rms phase jitter of less than 1ps (12kHz – 20MHz). This phase jitter performance meets the requirements of 1Gb/ 10Gb Ethernet, 1Gb, 2Gb, 4Gb and 10Gb Fibre Channel, and SONET up to OC48 . The FemtoClock PLL can also be bypassed if frequency multiplication is not required. For testing/debug purposes, de-assertion of the output enable pin will place both Q and nQ in a high impedance state.
Datasheet
Description
The 813001I is a dual VCXO + FemtoClock® Multiplier designed for use in Discrete PLL loops. Two selectable external VCXO crystals allow the device to be used in multi-rate applications, where a given line card can be switched, for example, between 1Gb Ethernet (125MHz system reference clock) and 1Gb Fibre Channel (106.25MHz system reference clock) modes. Of course, a multitude of other applications are also possible such as switching between 74.25MHz and 74.175824MHz for HDTV , switching between SONET , FEC and non FEC rates, etc. The 813001I is a two stage device – a VCXO followed by a FemtoClock PLL . The FemtoClock PLL can multiply the crystal frequency of the VCXO to provide an output frequency range of 40.83MHz to 640MHz, with a random rms phase jitter of less than 1ps (12kHz – 20MHz). This phase jitter performance meets the requirements of 1Gb/ 10Gb Ethernet, 1Gb, 2Gb, 4Gb and 10Gb Fibre Channel, and SONET up to OC48 . The FemtoClock PLL can also be bypassed if frequency multiplication is not required. For testing/debug purposes, de-assertion of the output enable pin will place both Q and nQ in a high impedance state.
Datasheet

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Dual VCXO W/3.3V,2.5V LVPECL FemtoClock PLL - 813001AGILFT - Integrated Device Technology
San Jose, CA, USA
Dual VCXO W/3.3V,2.5V LVPECL FemtoClock PLL
813001AGILFT
Dual VCXO W/3.3V,2.5V LVPECL FemtoClock PLL 813001AGILFT
The 813001I is a dual VCXO + FemtoClock® Multiplier designed for use in Discrete PLL loops. Two selectable external VCXO crystals allow the device to be used in multi-rate applications, where a given line card can be switched, for example, between 1Gb Ethernet (125MHz system reference clock) and 1Gb Fibre Channel (106.25MHz system reference clock) modes. Of course, a multitude of other applications are also possible such as switching between 74.25MHz and 74.175824MHz for HDTV , switching between SONET , FEC and non FEC rates, etc. The 813001I is a two stage device – a VCXO followed by a FemtoClock PLL . The FemtoClock PLL can multiply the crystal frequency of the VCXO to provide an output frequency range of 40.83MHz to 640MHz, with a random rms phase jitter of less than 1ps (12kHz – 20MHz). This phase jitter performance meets the requirements of 1Gb/ 10Gb Ethernet, 1Gb, 2Gb, 4Gb and 10Gb Fibre Channel, and SONET up to OC48 . The FemtoClock PLL can also be bypassed if frequency multiplication is not required. For testing/debug purposes, de-assertion of the output enable pin will place both Q and nQ in a high impedance state.

The 813001I is a dual VCXO + FemtoClock® Multiplier designed for use in Discrete PLL loops. Two selectable external VCXO crystals allow the device to be used in multi-rate applications, where a given line card can be switched, for example, between 1Gb Ethernet (125MHz system reference clock) and 1Gb Fibre Channel (106.25MHz system reference clock) modes. Of course, a multitude of other applications are also possible such as switching between 74.25MHz and 74.175824MHz for HDTV , switching between SONET , FEC and non FEC rates, etc. The 813001I is a two stage device – a VCXO followed by a FemtoClock PLL . The FemtoClock PLL can multiply the crystal frequency of the VCXO to provide an output frequency range of 40.83MHz to 640MHz, with a random rms phase jitter of less than 1ps (12kHz – 20MHz). This phase jitter performance meets the requirements of 1Gb/ 10Gb Ethernet, 1Gb, 2Gb, 4Gb and 10Gb Fibre Channel, and SONET up to OC48 . The FemtoClock PLL can also be bypassed if frequency multiplication is not required. For testing/debug purposes, de-assertion of the output enable pin will place both Q and nQ in a high impedance state.

Supplier's Site Datasheet

Technical Specifications

  Integrated Device Technology
Product Category IC Phase-locked Loops (PLL)
Product Number 813001AGILFT
Product Name Dual VCXO W/3.3V,2.5V LVPECL FemtoClock PLL
Bus Interface LVPECL; LVPECL
Package Type Surface Mount; TSSOP; TSSOP
Supply Voltage 3.3 volts
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