Nexperia B.V. Dual JK flip-flop with reset; negative-edge trigger 74HC107D-Q100J

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Dual JK flip-flop with reset; negative-edge trigger - 74HC107D-Q100J - Nexperia B.V.
Nijmegen, Netherlands
Dual JK flip-flop with reset; negative-edge trigger
74HC107D-Q100J
Dual JK flip-flop with reset; negative-edge trigger 74HC107D-Q100J
The 74HC107-Q100; 74HCT107-Q100 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs. The reset is an asynchronous active LOW input and operates independently of the clock input. The J and K inputs control the state changes of the flip-flops as described in the mode select function table. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from -40 °C to +85 °C and from -40 °C to +125 °C Wide supply voltage range from 2.0 V to 6.0 V CMOS low power dissipation High noise immunity Latch-up performance exceeds 100 mA per JESD 78 Class II Level B Complies with JEDEC standards: JESD8C (2.7 V to 3.6 V) JESD7A (2.0 V to 6.0 V) Input levels: For 74HC107-Q100: CMOS level For 74HCT107-Q100: TTL level ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

The 74HC107-Q100; 74HCT107-Q100 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs. The reset is an asynchronous active LOW input and operates independently of the clock input. The J and K inputs control the state changes of the flip-flops as described in the mode select function table. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC.

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.

Features and benefits

  • Automotive product qualification in accordance with AEC-Q100 (Grade 1)
    • Specified from -40 °C to +85 °C and from -40 °C to +125 °C
  • Wide supply voltage range from 2.0 V to 6.0 V
  • CMOS low power dissipation
  • High noise immunity
  • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
  • Complies with JEDEC standards:
    • JESD8C (2.7 V to 3.6 V)
    • JESD7A (2.0 V to 6.0 V)
  • Input levels:
    • For 74HC107-Q100: CMOS level
    • For 74HCT107-Q100: TTL level
  • ESD protection:
    • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
Supplier's Site Datasheet
Flip Flops - 1727-74HC107D-Q100JTR-ND - DigiKey
Thief River Falls, MN, United States
Flip Flop 2 Element JK Type 1 Bit Negative Edge 14-SOIC (0.154", 3.90mm Width)

Flip Flop 2 Element JK Type 1 Bit Negative Edge 14-SOIC (0.154", 3.90mm Width)

Supplier's Site Datasheet
Logic - Flip Flops - 74HC107D-Q100J - Lingto Electronic Limited
Shenzhen, China
Logic - Flip Flops
74HC107D-Q100J
Logic - Flip Flops 74HC107D-Q100J
IC FF JK TYPE DUAL 1BIT 14SO

IC FF JK TYPE DUAL 1BIT 14SO

Supplier's Site Datasheet
Integrated Circuits (ICs) - Logic - Flip Flops - 74HC107D-Q100J - Shenzhen Shengyu Electronics Technology Limited
Futian, China
Integrated Circuits (ICs) - Logic - Flip Flops
74HC107D-Q100J
Integrated Circuits (ICs) - Logic - Flip Flops 74HC107D-Q100J
IC FF JK TYPE DUAL 1BIT 14SO

IC FF JK TYPE DUAL 1BIT 14SO

Supplier's Site
 - 74HC107D-Q100J - Rochester Electronics
Newburyport, MA, United States
74HC107 - Dual JK flip-flop with reset; negative-edge trigger

74HC107 - Dual JK flip-flop with reset; negative-edge trigger

Supplier's Site Datasheet
Flip Flops - 74HC107D-Q100J - Quarktwin Technology Ltd.
Shenzhen, Guangdong, China
Flip Flops
74HC107D-Q100J
Flip Flops 74HC107D-Q100J
Flip Flop 2 Element JK Type 1 Bit Negative Edge 14-SOIC (0.154", 3.90mm Width)

Flip Flop 2 Element JK Type 1 Bit Negative Edge 14-SOIC (0.154", 3.90mm Width)

Supplier's Site Datasheet

Technical Specifications

  Nexperia B.V. DigiKey Lingto Electronic Limited Shenzhen Shengyu Electronics Technology Limited Rochester Electronics Quarktwin Technology Ltd.
Product Category Flip-Flops Flip-Flops Flip-Flops Flip-Flops Flip-Flops Flip-Flops
Product Number 74HC107D-Q100J 1727-74HC107D-Q100JTR-ND 74HC107D-Q100J 74HC107D-Q100J 74HC107D-Q100J 74HC107D-Q100J
Product Name Dual JK flip-flop with reset; negative-edge trigger Flip Flops Logic - Flip Flops Integrated Circuits (ICs) - Logic - Flip Flops Flip Flops
Flip-Flop Type J-K J-K J-K J-K
Triggering Negative-edge Triggered Negative-edge Triggered Negative-edge Triggered
Supply Voltage 2.5V; 3V; 3.3V; 3.6V; 5V; 2.0 - 6.0 2V ~ 6V 2V ~ 6V
Features ESD Protection
Propagation Delay 16 ns 27 ns
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