Microchip Technology, Inc. SONET/SDH System Synchronizer ZL30117

Description
The ZL30117 SONET/SDH Line Card Synchronizer is a highly integrated device that provides timing and synchronization for network interface cards. The DPLL is capable of locking to one of three input references and provides a wide variety of synchronized output clocks and frame pulses. Additional Features Synchronizes with standard telecom system references and synthesizes a wide variety of protected telecom line interface clocks that are compliant with Telcordia GR-253-CORE and ITU-T G.813 Internal APLL provides standard output clock frequencies up to 622.08 MHz that meet jitter requirements for interfaces up to OC-192/STM-64 Programmable output synthesizer generates clock frequencies from any multiple of 8 kHz up to 77.76 MHz in addition to 2 kHz Provides 3 reference inputs which support clock frequencies with any multiples of 8 kHz up to 77.76 MHz in addition to 2 kHz Supports automatic hitless reference switching, automatic mode selection (locked, free-run, holdover), and selectable loop bandwidth Generates several styles of output frame pulses with selectable pulse width, polarity, and frequency Flexible input reference monitoring automatically disqualifies references based on frequency and phase irregularities
Datasheet
Description
The ZL30117 SONET/SDH Line Card Synchronizer is a highly integrated device that provides timing and synchronization for network interface cards. The DPLL is capable of locking to one of three input references and provides a wide variety of synchronized output clocks and frame pulses. Additional Features Synchronizes with standard telecom system references and synthesizes a wide variety of protected telecom line interface clocks that are compliant with Telcordia GR-253-CORE and ITU-T G.813 Internal APLL provides standard output clock frequencies up to 622.08 MHz that meet jitter requirements for interfaces up to OC-192/STM-64 Programmable output synthesizer generates clock frequencies from any multiple of 8 kHz up to 77.76 MHz in addition to 2 kHz Provides 3 reference inputs which support clock frequencies with any multiples of 8 kHz up to 77.76 MHz in addition to 2 kHz Supports automatic hitless reference switching, automatic mode selection (locked, free-run, holdover), and selectable loop bandwidth Generates several styles of output frame pulses with selectable pulse width, polarity, and frequency Flexible input reference monitoring automatically disqualifies references based on frequency and phase irregularities
Datasheet

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SONET/SDH System Synchronizer - ZL30117 - Microchip Technology, Inc.
Chandler, AZ, United States
SONET/SDH System Synchronizer
ZL30117
SONET/SDH System Synchronizer ZL30117
The ZL30117 SONET/SDH Line Card Synchronizer is a highly integrated device that provides timing and synchronization for network interface cards. The DPLL is capable of locking to one of three input references and provides a wide variety of synchronized output clocks and frame pulses. Additional Features Synchronizes with standard telecom system references and synthesizes a wide variety of protected telecom line interface clocks that are compliant with Telcordia GR-253-CORE and ITU-T G.813 Internal APLL provides standard output clock frequencies up to 622.08 MHz that meet jitter requirements for interfaces up to OC-192/STM-64 Programmable output synthesizer generates clock frequencies from any multiple of 8 kHz up to 77.76 MHz in addition to 2 kHz Provides 3 reference inputs which support clock frequencies with any multiples of 8 kHz up to 77.76 MHz in addition to 2 kHz Supports automatic hitless reference switching, automatic mode selection (locked, free-run, holdover), and selectable loop bandwidth Generates several styles of output frame pulses with selectable pulse width, polarity, and frequency Flexible input reference monitoring automatically disqualifies references based on frequency and phase irregularities

The ZL30117 SONET/SDH Line Card Synchronizer is a highly integrated device that provides timing and synchronization for network interface cards. The DPLL is capable of locking to one of three input references and provides a wide variety of synchronized output clocks and frame pulses.

Additional Features

  • Synchronizes with standard telecom system references and synthesizes a wide variety of protected telecom line interface clocks that are compliant with Telcordia GR-253-CORE and ITU-T G.813
  • Internal APLL provides standard output clock frequencies up to 622.08 MHz that meet jitter requirements for interfaces up to OC-192/STM-64
  • Programmable output synthesizer generates clock frequencies from any multiple of 8 kHz up to 77.76 MHz in addition to 2 kHz
  • Provides 3 reference inputs which support clock frequencies with any multiples of 8 kHz up to 77.76 MHz in addition to 2 kHz
  • Supports automatic hitless reference switching, automatic mode selection (locked, free-run, holdover), and selectable loop bandwidth
  • Generates several styles of output frame pulses with selectable pulse width, polarity, and frequency
  • Flexible input reference monitoring automatically disqualifies references based on frequency and phase irregularities
Supplier's Site Datasheet

Technical Specifications

  Microchip Technology, Inc.
Product Category Network Clock Sources
Product Number ZL30117
Product Name SONET/SDH System Synchronizer
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