The ZL30159 single PLL rate converter is part of Microchip's ClockCenter platform and can synchronize to any clock rate from 1 Hz (1pps) to 750 MHz. The conversion from 1pps is especially useful for GPS clock generation to 25MHz or 156.25MHz. The ZL30159 includes a high precision synthesizer that can generate any clock rate from 1Hz to 177.5 MHz with jitter below 1ps.
Additional Features
Precision synthesizer generates any clock-rate from 1 Hz to 177.5 MHz with jitter below 1ps
Programmable digital PLL synchronize to any clock rate from 1 Hz (1 pps) to 750 MHz
Input reference configurable as single ended LVCMOS (up to 177.5 MHz) or differential LVPECL (up to 750 MHz)
Flexible two-stage architecture translates between arbitrary data rates, line coding rates and FEC rates
Programmable Digital PLL loop filter: 30 mHz, 14 Hz, 28 Hz, 56 Hz, 112 Hz, 224 Hz, 448 Hz or 896 Hz
Two LVCMOS outputs —from 1 Hz (1 pps) to 177.5 MHz
Operates from a single crystal resonator or clock oscillator
Customer defined default device configuration, including input/output frequencies, is available via OTP(One Time Programmable) memory
Dynamically configurable via SPI/I2C interface and volatile configuration registers
Applications
• General purpose clock rate translator
• GPS receiver clock synthesizer
The ZL30159 single PLL rate converter is part of Microchip's ClockCenter platform and can synchronize to any clock rate from 1 Hz (1pps) to 750 MHz. The conversion from 1pps is especially useful for GPS clock generation to 25MHz or 156.25MHz. The ZL30159 includes a high precision synthesizer that can generate any clock rate from 1Hz to 177.5 MHz with jitter below 1ps.
Additional Features
- Precision synthesizer generates any clock-rate from 1 Hz to 177.5 MHz with jitter below 1ps
- Programmable digital PLL synchronize to any clock rate from 1 Hz (1 pps) to 750 MHz
- Input reference configurable as single ended LVCMOS (up to 177.5 MHz) or differential LVPECL (up to 750 MHz)
- Flexible two-stage architecture translates between arbitrary data rates, line coding rates and FEC rates
- Programmable Digital PLL loop filter: 30 mHz, 14 Hz, 28 Hz, 56 Hz, 112 Hz, 224 Hz, 448 Hz or 896 Hz
- Two LVCMOS outputs —from 1 Hz (1 pps) to 177.5 MHz
- Operates from a single crystal resonator or clock oscillator
- Customer defined default device configuration, including input/output frequencies, is available via OTP(One Time Programmable) memory
- Dynamically configurable via SPI/I2C interface and volatile configuration registers
- Applications
- • General purpose clock rate translator
- • GPS receiver clock synthesizer
