- Trained on our vast library of engineering resources.

Nexperia B.V. Single D-type flip-flop with reset; positive-edge trigger 74LVC1G175GV-Q100H

Request a Quote Datasheet

Suppliers

Company
Product
Description
Supplier Links
Single D-type flip-flop with reset; positive-edge trigger - 74LVC1G175GV-Q100H - Nexperia B.V.
Nijmegen, Netherlands
Single D-type flip-flop with reset; positive-edge trigger
74LVC1G175GV-Q100H
Single D-type flip-flop with reset; positive-edge trigger 74LVC1G175GV-Q100H
The 74LVC1G175-Q100 is a low-power, low-voltage single positive edge triggered D-type flip-flop with individual data (D) input, clock (CP) input, master reset (MR) input, and Q output. The master reset (MR) is an asynchronous active LOW input and operates independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D input must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. The inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and fall times. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from -40 °C to +85 °C and from -40 °C to +125 °C Wide supply voltage range from 1.65 V to 5.5 V High noise immunity Overvoltage tolerant inputs to 5.5 V ±24 mA output drive (VCC = 3.0 V) CMOS low power dissipation Direct interface with TTL levels IOFF circuitry provides partial Power-down mode operation Latch-up performance exceeds 250 mA Complies with JEDEC standard: JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8C (2.7 V to 3.6 V) JESD36 (4.5 V to 5.5 V) ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

The 74LVC1G175-Q100 is a low-power, low-voltage single positive edge triggered D-type flip-flop with individual data (D) input, clock (CP) input, master reset (MR) input, and Q output. The master reset (MR) is an asynchronous active LOW input and operates independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D input must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. The inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and fall times.

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.

Features and benefits

  • Automotive product qualification in accordance with AEC-Q100 (Grade 1)
    • Specified from -40 °C to +85 °C and from -40 °C to +125 °C
  • Wide supply voltage range from 1.65 V to 5.5 V
  • High noise immunity
  • Overvoltage tolerant inputs to 5.5 V
  • ±24 mA output drive (VCC = 3.0 V)
  • CMOS low power dissipation
  • Direct interface with TTL levels
  • IOFF circuitry provides partial Power-down mode operation
  • Latch-up performance exceeds 250 mA
  • Complies with JEDEC standard:
    • JESD8-7 (1.65 V to 1.95 V)
    • JESD8-5 (2.3 V to 2.7 V)
    • JESD8C (2.7 V to 3.6 V)
    • JESD36 (4.5 V to 5.5 V)
  • ESD protection:
    • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
Supplier's Site Datasheet
Futian, Shenzhen, China
Logic ICs >> Flip Flops
74LVC1G175GV-Q100H
Logic ICs >> Flip Flops 74LVC1G175GV-Q100H
1.65V~5.5V 200MHz 4ns@5V,50pF D-Type 1 1 40uA SC-74 Flip Flops ROHS

1.65V~5.5V 200MHz 4ns@5V,50pF D-Type 1 1 40uA SC-74 Flip Flops ROHS

Supplier's Site Datasheet
Flip Flops - 74LVC1G175GV-Q100H-ND - DigiKey
Thief River Falls, MN, United States
Flip Flop 1 Element D-Type 1 Bit Positive Edge SC-74, SOT-457

Flip Flop 1 Element D-Type 1 Bit Positive Edge SC-74, SOT-457

Supplier's Site Datasheet
Flip Flops - 74LVC1G175GV-Q100H - Quarktwin Technology Ltd.
Shenzhen, Guangdong, China
Flip Flop 1 Element D-Type 1 Bit Positive Edge SC-74, SOT-457

Flip Flop 1 Element D-Type 1 Bit Positive Edge SC-74, SOT-457

Supplier's Site Datasheet
Integrated Circuits (ICs) - Logic - Flip Flops - 74LVC1G175GV-Q100H - Shenzhen Shengyu Electronics Technology Limited
Futian, China
Integrated Circuits (ICs) - Logic - Flip Flops
74LVC1G175GV-Q100H
Integrated Circuits (ICs) - Logic - Flip Flops 74LVC1G175GV-Q100H
IC FF D-TYPE SNGL 1BIT 6TSOP

IC FF D-TYPE SNGL 1BIT 6TSOP

Supplier's Site
Logic - Flip Flops - 74LVC1G175GV-Q100H - Lingto Electronic Limited
Shenzhen, China
Logic - Flip Flops
74LVC1G175GV-Q100H
Logic - Flip Flops 74LVC1G175GV-Q100H
IC FF D-TYPE SNGL 1BIT 6TSOP

IC FF D-TYPE SNGL 1BIT 6TSOP

Supplier's Site Datasheet

Technical Specifications

  Nexperia B.V. LCSC Electronics Technology (HK) Limited DigiKey Quarktwin Technology Ltd. Shenzhen Shengyu Electronics Technology Limited Lingto Electronic Limited
Product Category Flip-Flops Flip-Flops Flip-Flops Flip-Flops Flip-Flops Flip-Flops
Product Number 74LVC1G175GV-Q100H 74LVC1G175GV-Q100H 74LVC1G175GV-Q100H-ND 74LVC1G175GV-Q100H 74LVC1G175GV-Q100H 74LVC1G175GV-Q100H
Product Name Single D-type flip-flop with reset; positive-edge trigger Logic ICs >> Flip Flops Flip Flops Flip Flops Integrated Circuits (ICs) - Logic - Flip Flops Logic - Flip Flops
Flip-Flop Type D D D D
Triggering Positive-edge Triggered Positive-edge Triggered
Supply Voltage 1.8V; 2.5V; 3V; 3.3V; 3.6V; 5V; 1.65 - 5.5 1.65V~5.5V 1.65V ~ 5.5V 1.65V ~ 5.5V
Features ESD Protection
Propagation Delay 3.1 ns 4 ns 4 ns
Unlock Full Specs
to access all available technical data

Similar Products

Quad D-type flip-flop with reset; positive-edge trigger - 74HC175D,653 - Nexperia B.V.
Specs
Flip-Flop Type D
Triggering Positive-edge Triggered
Supply Voltage 2.5V; 3V; 3.3V; 3.6V; 5V; 2.0 - 6.0
View Details
7 suppliers
Low-power D-type flip-flop; positive-edge trigger; 3-state - 74AUP1G374GW-Q100H - Nexperia B.V.
Specs
Flip-Flop Type D
Triggering Positive-edge Triggered
Supply Voltage 0.8 - 3.6
View Details
5 suppliers
Dual D-type flip-flop with set and reset; positive-edge trigger - 74LV74D-Q100J - Nexperia B.V.
Specs
Flip-Flop Type D
Triggering Positive-edge Triggered
Supply Voltage 1.2V; 1.5V; 1.8V; 2.5V; 3V; 3.3V; 3.6V; 5V; 1.0 - 5.5
View Details
6 suppliers
Dual D-type flip-flop with set and reset; positive-edge trigger - 74LV74D,118 - Nexperia B.V.
Specs
Flip-Flop Type D
Triggering Positive-edge Triggered
Supply Voltage 1.2V; 1.5V; 1.8V; 2.5V; 3V; 3.3V; 3.6V; 5V; 1.0 - 5.5
View Details
6 suppliers