The SY89826L is a precision fanout buffer with 22 differential LVDS (Low Voltage Differential Swing) output pairs. The part is designed for use in low voltage 3.3V applications that require a large number of outputs to drive precisely aligned, ultra low-skew signals to their destination.The input is multiplexed from either LVDS or LVPECL (Low Voltage Positive Emitter Coupled Logic) by the CLK_SEL pin. The OE (Output Enable) is synchronous so that the outputs will only be enabled/disabled when they are already in the LOW state. This avoids any chance of generating a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control.The SY89826L features a low pin-to-pin skew of less than 50ps--performance previously unachievable in a standard product having such a high number of outputs.The SY89826L is available in a single space saving package, enabling a lower overall cost solution.
Additional Features
High-performance, 1GHz LVDS fanout buffer/ translator
22 differential LVDS output pairs
Guaranteed AC parameters over temperature and voltage:
>1GHz fMAX
<50ps within device skew
<400ps tr/tf time
Low jitter performance
<1psrms cycle-to-cycle jitter
<1ps (pk-pk) total jitter
2:1 mux input accepts LVDS and LVPECL
3.3V supply voltage
LVDS input includes internal 100Ω termination
Output enable function
Available in a 64-Pin EPAD-TQFP
The SY89826L is a precision fanout buffer with 22 differential LVDS (Low Voltage Differential Swing) output pairs. The part is designed for use in low voltage 3.3V applications that require a large number of outputs to drive precisely aligned, ultra low-skew signals to their destination.The input is multiplexed from either LVDS or LVPECL (Low Voltage Positive Emitter Coupled Logic) by the CLK_SEL pin. The OE (Output Enable) is synchronous so that the outputs will only be enabled/disabled when they are already in the LOW state. This avoids any chance of generating a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control.The SY89826L features a low pin-to-pin skew of less than 50ps--performance previously unachievable in a standard product having such a high number of outputs.The SY89826L is available in a single space saving package, enabling a lower overall cost solution.
Additional Features
- High-performance, 1GHz LVDS fanout buffer/ translator
- 22 differential LVDS output pairs
- Guaranteed AC parameters over temperature and voltage:
- >1GHz fMAX
- <50ps within device skew
- <400ps tr/tf time
- Low jitter performance
- <1psrms cycle-to-cycle jitter
- <1ps (pk-pk) total jitter
- 2:1 mux input accepts LVDS and LVPECL
- 3.3V supply voltage
- LVDS input includes internal 100Ω termination
- Output enable function
- Available in a 64-Pin EPAD-TQFP
