Microchip Technology, Inc. eXtreme Low Power MCU PIC24FJ32GP202

The PIC24FJ ‘GP2/GU2’ family offers up to 64KB of ECC Flash, 8KB of RAM, along with several core independent peripherals (CIPs) and Full Speed USB 2.0 Host/Device/OTG. With sleep current down to a few hundreds of nA while retaining the complete RAM content, the ‘GP2/GU2’’ family is perfect for extending your battery life in any portable applications. Supported in the MPLAB® Code Configurator (MCC) tool, the development time gets significantly reduced by allowing you to configure the devices and libraries with just a few clicks. To address the evolving focus on safety and security, these MCUs offer hardware safety features and secure protection schemes, simplifying design of smart, safe, secure and connected applications. These MCUs feature protection schemes such as Flash OTP by ICSP™ Write Inhibit which allows the entire Flash to be configured as One-Time-Programmabl e (OTP) memory and CodeGuard™ Flash Security which facilitates to segment the memory and implement access restrictions. These features together with our CryptoAuthentication ™ chips enable you to implement security in your applications. Offering an extended operating temperature of up to 125°C with AEC Q100 Grade 1 qualification, this family is also well suited for Automotive and Industrial applications. A range of hardware safety features on this family helps you develop robust designs operating in extreme conditions. With a high-level of analog integration, this family simplifies sensor interfacing and analog measurement, while reducing the overall system BoM cost. Additional Features Core and Operating Conditions 2.0V to 3.6V, -40°C to 125°C, up to 16 MIPS operation Single-cycle instruction execution 16 x 16 Hardware Multiply, and 32-bit x 16-bit Hardware Divider C compiler optimized instruction set system AEC Q100 Grade 1 qualification eXtreme Low Power Ultra-low-power operation with sleep current down to nA with full RAM retention A range of power-saving modes to reduce current consumption, while balancing performance: PMD bits, DOZE, Idle, Sleep and Retention Sleep modes A range of Core Independent Peripherals (CIPs) that operate in power saving modes, while off-loading the Central Processing Unit (CPU) Secure Protection Features Flash ‘One Time Programming’ (OTP) by ICSP™ Write Inhibit that offers an ability to disable Flash erase/write/debug operations CodeGuard™ Flash protection to manage memory partitions and access restrictions 120-bit Unique Device ID, 256 bytes User OTP and the above protection schemes make an ideal combination of complementary features to implement security together with the CryptoAuthentication ™ devices in a secure application Hardware Safety Features Flash with Error Correction Code (ECC) and Fault Injection for memory integrity check (Single error correction and Double error detection) Dead-Man Timer (DMT) clocked by instruction fetches for monitoring the health of software Windowed WatchDog Timer (WWDT) for system supervision CodeGuard™ Flash protection for memory partition and access restriction Fail-Safe Clock Monitor (FSCM) for clock fault management Enhanced Programmable Cyclic Redundancy Check (CRC), Programmable High-Low Voltage Detect (HLVD), Brown-out Reset (BOR) and Power-on Reset (POR) Class B Safety Library, IEC 60730 Advanced Integrated Analog Up to 14-Channel, 400Ksps, 10/12-Bit Analog-to-Digital Converter (ADC) Low-voltage boost for input Bandgap reference input feature Core Independent windowed threshold compare feature Auto-scan feature Operation in power-saving modes Three Analog Comparators with input multiplexing and programmable reference voltage generators Timer/Counters/Outpu t Compare/Input Capture/Pulse Width Modulation 3x 16-bit or 1x 32-bit dedicated timer/counters 10x PWM or Output Compare (OC) outputs with 5 independent timer bases – Multiple Capture Compare PWMs (MCCPs) 5x Input Captures (IC) – Multiple Capture Compare PWMs (MCCPs) A total of 13x 16-bit or 3x 32-bit timer/counters Hardware Real-Time Clock Calendar (RTCC) with Timestamping Core Independent Peripherals 4x Configurable Logic Cells (CLCs) 5x Multiple Capture Compare PWMs (MCCPs) ADC controller with threshold compare and automatic triggers Direct Memory Access (DMA) with 2 channels, supporting UART, SPI, ADC, and more Communication Interfaces 2x UARTs supporting LIN/J2602 and IrDA® 2x SPI/I2S, up to 25 MHz operation 2x I2C Master and Slave w/Address Masking, PMBus™ and IPMI support Clock Management On-chip 8 MHz Fast RC (FRC), and 32 kHz Low-Power RC (LPRC) and Secondary (SOSC) oscillators Programmable PLL with external oscillator clock sources and Reference Clock Output (REFO) Fail-Safe Clock Monitor (FSCM) Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) supporting two-speed start-up Special Features and Debugger Development Support MPLAB Code Configurator (MCC) support Peripheral Pin Select (PPS) for flexible pin mapping Configurable interrupt-on change on all IOs In-Circuit Serial Programming™ (ICSP™) and In-Circuit Emulation (ICE) via 2-pins JTAG Boundary Scan Support