Integrated Device Technology FemtoClock NG Jitter Attenuator and Clock Synthesizer 8V44N4614NLGI

Description
The 8V44N4614 is a FemtoClock® NG Clock Generator. The device has been designed for frequency generation in high-performance systems such wireless base-band boards, for instance to drive the reference clock inputs of processors, PHY , switch and SerDes devices. The device is very flexible in frequency programming. It allows to generate the clock frequencies of 156.25MHz, 125MHz, 100MHz and 25MHz individually at three output banks. One output bank supports configurable LVDS , LVPECL , the other two output banks support LVCMOS output levels. All outputs are synchronized on the incident rising edge, regardless of the selected output frequency. Selective single-ended LVCMOS outputs can be configured to invert the output phase, effectively forming differential LVCMOS output pairs for noise reduction. The PLL reference signal is either a 25MHz, 50MHz, 100MHz or 200MHz differential or single-ended clock. The device is optimized to deliver excellent period and cycle-to-cycle jitter performance, combined with good phase noise performance, and high power supply noise rejection. The device is configured through an SPI serial interface. Outputs can be configured to any of the available output frequencies. Two hardware pins are available for selecting pre-set output enable/disable configurations. In each of these pre-set configurations, each output can be enabled/disabled individually. A separate test mode is available for an increase or decrease of the output frequencies in 19.53125ppm steps independent on the input frequency. The device is packaged in a lead-free (RoHS 6) 48-lead VFQFN package. The extended temperature range supports wireless infrastructure, telecommunication and networking end equipment requirements.
Datasheet
Description
The 8V44N4614 is a FemtoClock® NG Clock Generator. The device has been designed for frequency generation in high-performance systems such wireless base-band boards, for instance to drive the reference clock inputs of processors, PHY , switch and SerDes devices. The device is very flexible in frequency programming. It allows to generate the clock frequencies of 156.25MHz, 125MHz, 100MHz and 25MHz individually at three output banks. One output bank supports configurable LVDS , LVPECL , the other two output banks support LVCMOS output levels. All outputs are synchronized on the incident rising edge, regardless of the selected output frequency. Selective single-ended LVCMOS outputs can be configured to invert the output phase, effectively forming differential LVCMOS output pairs for noise reduction. The PLL reference signal is either a 25MHz, 50MHz, 100MHz or 200MHz differential or single-ended clock. The device is optimized to deliver excellent period and cycle-to-cycle jitter performance, combined with good phase noise performance, and high power supply noise rejection. The device is configured through an SPI serial interface. Outputs can be configured to any of the available output frequencies. Two hardware pins are available for selecting pre-set output enable/disable configurations. In each of these pre-set configurations, each output can be enabled/disabled individually. A separate test mode is available for an increase or decrease of the output frequencies in 19.53125ppm steps independent on the input frequency. The device is packaged in a lead-free (RoHS 6) 48-lead VFQFN package. The extended temperature range supports wireless infrastructure, telecommunication and networking end equipment requirements.
Datasheet

Suppliers

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FemtoClock NG Jitter Attenuator and Clock Synthesizer - 8V44N4614NLGI - Integrated Device Technology
San Jose, CA, USA
FemtoClock NG Jitter Attenuator and Clock Synthesizer
8V44N4614NLGI
FemtoClock NG Jitter Attenuator and Clock Synthesizer 8V44N4614NLGI
The 8V44N4614 is a FemtoClock® NG Clock Generator. The device has been designed for frequency generation in high-performance systems such wireless base-band boards, for instance to drive the reference clock inputs of processors, PHY , switch and SerDes devices. The device is very flexible in frequency programming. It allows to generate the clock frequencies of 156.25MHz, 125MHz, 100MHz and 25MHz individually at three output banks. One output bank supports configurable LVDS , LVPECL , the other two output banks support LVCMOS output levels. All outputs are synchronized on the incident rising edge, regardless of the selected output frequency. Selective single-ended LVCMOS outputs can be configured to invert the output phase, effectively forming differential LVCMOS output pairs for noise reduction. The PLL reference signal is either a 25MHz, 50MHz, 100MHz or 200MHz differential or single-ended clock. The device is optimized to deliver excellent period and cycle-to-cycle jitter performance, combined with good phase noise performance, and high power supply noise rejection. The device is configured through an SPI serial interface. Outputs can be configured to any of the available output frequencies. Two hardware pins are available for selecting pre-set output enable/disable configurations. In each of these pre-set configurations, each output can be enabled/disabled individually. A separate test mode is available for an increase or decrease of the output frequencies in 19.53125ppm steps independent on the input frequency. The device is packaged in a lead-free (RoHS 6) 48-lead VFQFN package. The extended temperature range supports wireless infrastructure, telecommunication and networking end equipment requirements.

The 8V44N4614 is a FemtoClock® NG Clock Generator. The device has been designed for frequency generation in high-performance systems such wireless base-band boards, for instance to drive the reference clock inputs of processors, PHY , switch and SerDes devices. The device is very flexible in frequency programming. It allows to generate the clock frequencies of 156.25MHz, 125MHz, 100MHz and 25MHz individually at three output banks. One output bank supports configurable LVDS , LVPECL , the other two output banks support LVCMOS output levels. All outputs are synchronized on the incident rising edge, regardless of the selected output frequency. Selective single-ended LVCMOS outputs can be configured to invert the output phase, effectively forming differential LVCMOS output pairs for noise reduction. The PLL reference signal is either a 25MHz, 50MHz, 100MHz or 200MHz differential or single-ended clock.
The device is optimized to deliver excellent period and cycle-to-cycle jitter performance, combined with good phase noise performance, and high power supply noise rejection.
The device is configured through an SPI serial interface. Outputs can be configured to any of the available output frequencies. Two hardware pins are available for selecting pre-set output enable/disable configurations. In each of these pre-set configurations, each output can be enabled/disabled individually. A separate test mode is available for an increase or decrease of the output frequencies in 19.53125ppm steps independent on the input frequency. The device is packaged in a lead-free (RoHS 6) 48-lead VFQFN package. The extended temperature range supports wireless infrastructure, telecommunication and networking end equipment requirements.

Supplier's Site Datasheet

Technical Specifications

  Integrated Device Technology
Product Category IC Phase-locked Loops (PLL)
Product Number 8V44N4614NLGI
Product Name FemtoClock NG Jitter Attenuator and Clock Synthesizer
Bus Interface LVPECL; LVDS; LVDS,LVPECL,LVCMOS
Package Type Surface Mount; VFQFPN
Supply Voltage 3.3 volts
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