Integrated Device Technology 1:8 LVDS Fanout Buffer with 2-Input Multiplexer for 1PPS Applications 8V34S208NLGI8

The 8V34S208 is a differential 1:8 LVDS fanout buffer with a 2:1 input multiplexer. The device accepts DC to 250MHz clock and data signals and is designed for 1Hz clock / 1PPS , 2kHz and 8kHz signal distribution. Controlled by the input mode selection pin, the differential input stages accept both rectangular or sinusoidal signals. The 8V34S208 also provides level translated LVCMOS / LVTTL outputs which are copies of the individual differential inputs CLKA and CLKB . The propagation delay of the device is very low, providing an ideal solution for clock distribution circuits with tight phase alignment requirements. The multiplexer select pin ( SEL ) allows to select one out of two input signals, which is copied to the four differential outputs.