Integrated Device Technology Low Skew,Dual,Programmable 1-to-2 Differential-to-LVDS,LVPECL Fanout Buffer 854S204BGILFT

Description
The 854S204I is a low skew, high performance dual, programmable 1-to-2 Differential-to- LVDS , LVPECL Fanout Buffer. The PCLKx, nPCLKx pairs can accept most standard differential input levels. With the selection of SEL_OUT signal, outputs can be selected be to either LVDS or LVPECL levels. The 854S204I is characterized to operate from either a 2.5V or a 3.3V power supply. Guaranteed output and bank skew characteristics make the 854S204I ideal for those clock distribution applications demanding well defined performance and repeatability. The 854S204I is a low skew, high performance dual, programmable 1-to-2 Differential-to- LVDS , LVPECL Fanout Buffer. The PCLKx, nPCLKx pairs can accept most standard differential input levels. With the selection of SEL_OUT signal, outputs can be selected be to either LVDS or LVPECL levels. The 854S204I is characterized to operate from either a 2.5V or a 3.3V power supply. Guaranteed output and bank skew characteristics make the 854S204I ideal for those clock distribution applications demanding well defined performance and repeatability.
Datasheet
Description
The 854S204I is a low skew, high performance dual, programmable 1-to-2 Differential-to- LVDS , LVPECL Fanout Buffer. The PCLKx, nPCLKx pairs can accept most standard differential input levels. With the selection of SEL_OUT signal, outputs can be selected be to either LVDS or LVPECL levels. The 854S204I is characterized to operate from either a 2.5V or a 3.3V power supply. Guaranteed output and bank skew characteristics make the 854S204I ideal for those clock distribution applications demanding well defined performance and repeatability. The 854S204I is a low skew, high performance dual, programmable 1-to-2 Differential-to- LVDS , LVPECL Fanout Buffer. The PCLKx, nPCLKx pairs can accept most standard differential input levels. With the selection of SEL_OUT signal, outputs can be selected be to either LVDS or LVPECL levels. The 854S204I is characterized to operate from either a 2.5V or a 3.3V power supply. Guaranteed output and bank skew characteristics make the 854S204I ideal for those clock distribution applications demanding well defined performance and repeatability.
Datasheet

Suppliers

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Supplier Links
Low Skew,Dual,Programmable 1-to-2 Differential-to-LVDS,LVPECL Fanout Buffer - 854S204BGILFT - Integrated Device Technology
San Jose, CA, USA
Low Skew,Dual,Programmable 1-to-2 Differential-to-LVDS,LVPECL Fanout Buffer
854S204BGILFT
Low Skew,Dual,Programmable 1-to-2 Differential-to-LVDS,LVPECL Fanout Buffer 854S204BGILFT
The 854S204I is a low skew, high performance dual, programmable 1-to-2 Differential-to- LVDS , LVPECL Fanout Buffer. The PCLKx, nPCLKx pairs can accept most standard differential input levels. With the selection of SEL_OUT signal, outputs can be selected be to either LVDS or LVPECL levels. The 854S204I is characterized to operate from either a 2.5V or a 3.3V power supply. Guaranteed output and bank skew characteristics make the 854S204I ideal for those clock distribution applications demanding well defined performance and repeatability. The 854S204I is a low skew, high performance dual, programmable 1-to-2 Differential-to- LVDS , LVPECL Fanout Buffer. The PCLKx, nPCLKx pairs can accept most standard differential input levels. With the selection of SEL_OUT signal, outputs can be selected be to either LVDS or LVPECL levels. The 854S204I is characterized to operate from either a 2.5V or a 3.3V power supply. Guaranteed output and bank skew characteristics make the 854S204I ideal for those clock distribution applications demanding well defined performance and repeatability.

The 854S204I is a low skew, high performance dual, programmable 1-to-2 Differential-to- LVDS , LVPECL Fanout Buffer. The PCLKx, nPCLKx pairs can accept most standard differential input levels. With the selection of SEL_OUT signal, outputs can be selected be to either LVDS or LVPECL levels. The 854S204I is characterized to operate from either a 2.5V or a 3.3V power supply. Guaranteed output and bank skew characteristics make the 854S204I ideal for those clock distribution applications demanding well defined performance and repeatability. The 854S204I is a low skew, high performance dual, programmable 1-to-2 Differential-to- LVDS , LVPECL Fanout Buffer. The PCLKx, nPCLKx pairs can accept most standard differential input levels. With the selection of SEL_OUT signal, outputs can be selected be to either LVDS or LVPECL levels. The 854S204I is characterized to operate from either a 2.5V or a 3.3V power supply. Guaranteed output and bank skew characteristics make the 854S204I ideal for those clock distribution applications demanding well defined performance and repeatability.

Supplier's Site Datasheet

Technical Specifications

  Integrated Device Technology
Product Category IC Interfaces
Product Number 854S204BGILFT
Product Name Low Skew,Dual,Programmable 1-to-2 Differential-to-LVDS,LVPECL Fanout Buffer
Technology LVDS
Device Type Buffer
Supply Voltage 2.5V; 3.3V; Other; 2.50-2.50,3.30-3.30
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