Integrated Device Technology Low Skew,1-to-4 Differential-to-LVDS Fanout Buffer 8543BGLFT

The 8543 is a low skew, high performance 1-to-4 Differential-to- LVDS Clock Fanout Buffer. Utilizing Low Voltage Differential Signaling ( LVDS ) the 8543 provides a low power, low noise, solution for distributing clock signals over controlled impedances of 100?. The 8543 has two selectable clock inputs. The CLK , nCLK pair can accept most standard differential input levels. The PCLK , nPCLK pair can accept LVPECL , CML , or SSTL input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertio n of the clock enable pin. Guaranteed output and part-to-part skew characteristics make the 8543 ideal for those applications demanding well defined performance and repeatability.