The 8524 is a low skew, 1-to-22 Differential-to- HSTL Fanout Buffer . The 8524 has two selectable clock inputs. The CLK , nCLK pair can accept most standard differential input levels. The PCLK , nPCLK pair can accept LVPECL , CML , or SSTL input levels. The device is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertio
n of the OE pin. The 8524's low output and part-to-part skew characteristics make it ideal for workstation, server, and other high performance clock distribution applications.
The 8524 is a low skew, 1-to-22 Differential-to- HSTL Fanout Buffer . The 8524 has two selectable clock inputs. The CLK , nCLK pair can accept most standard differential input levels. The PCLK , nPCLK pair can accept LVPECL , CML , or SSTL input levels. The device is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the OE pin. The 8524's low output and part-to-part skew characteristics make it ideal for workstation, server, and other high performance clock distribution applications.
