The 85105I is a low skew, high performance 1-to-5 Differential-to-0.7V HCSL Fanout Buffer. The 85105I has two selectable clock inputs. The CLK0 , nCLK0 pair can accept most standard differential input levels. The single-ended CLK1 can accept LVCMOS or LVTTL input levels. The clock enable is internally synchronized to eliminate runt clock pulses on the outputs during asynchronous assertion/deassertio
n of the clock enable pin. Guaranteed output and part-to-part skew characteristics make the 85105I ideal for those applications demanding well defined performance and repeatability.
The 85105I is a low skew, high performance 1-to-5 Differential-to-0.7V HCSL Fanout Buffer. The 85105I has two selectable clock inputs. The CLK0 , nCLK0 pair can accept most standard differential input levels. The single-ended CLK1 can accept LVCMOS or LVTTL input levels. The clock enable is internally synchronized to eliminate runt clock pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. Guaranteed output and part-to-part skew characteristics make the 85105I ideal for those applications demanding well defined performance and repeatability.
