Integrated Device Technology Synchronous Ethernet SETS for 10GbE and 40GbE 82V3910AUG8

Description
IDT 82V3910 is a single chip synchronous equipment timing source ( SETS ) for synchronous Ethernet (SyncE). The 82V3910 complies with ITU -T G.8262 for EEC -Options 1 and 2; and G.813 for SEC -Options 1 and 2; and it is suitable for SyncE, SONET and SDH equipment. Its ultra-low jitter generation makes it particularly suitable for single-board systems where the SETS directly times 10GBASE -R, 10GBASE -W, OC -192/ STM -64 or 40GBASE -R PHYs. The high-integration architecture minimizes component count and board space by including a “T0” G.8262 compliant digital PLL ( DPLL ); and a “T4” rate converting DPLL to provide recovered line timing to a local Building Integrated Timing Supply ( BITS ) or Synchronization Supply Unit ( SSU ). Two independent jitter attenuating analog PLLs (APLLs) are also integrated; these APLLs generate clocks with jitter below 0.3 ps RMS over the 10 kHz to 20 MHz integration range and can be used to directly time 10GbE or 40GbE network PHYs. The DPLLs lock to a wide variety of telecom and Ethernet reference frequencies and suppress incoming timing faults to generate highly-reliable output clocks for optimal network performance. The T0 DPLL can lock directly to a one pulse per second (1 PPS ) reference enabling the host system to use a low-cost GPS receiver for synchronization. IDT 82V3910 offers a solution optimized for use in Ethernet switches, routers, multiservice switching platforms, wireless backhaul equipment and other communications infrastructure. IDT 82V3910 is available in a 196-ball 15 x 15 mm CABGA package and supports standard industrial temperature range from -40degC to +85degC.
Datasheet
Description
IDT 82V3910 is a single chip synchronous equipment timing source ( SETS ) for synchronous Ethernet (SyncE). The 82V3910 complies with ITU -T G.8262 for EEC -Options 1 and 2; and G.813 for SEC -Options 1 and 2; and it is suitable for SyncE, SONET and SDH equipment. Its ultra-low jitter generation makes it particularly suitable for single-board systems where the SETS directly times 10GBASE -R, 10GBASE -W, OC -192/ STM -64 or 40GBASE -R PHYs. The high-integration architecture minimizes component count and board space by including a “T0” G.8262 compliant digital PLL ( DPLL ); and a “T4” rate converting DPLL to provide recovered line timing to a local Building Integrated Timing Supply ( BITS ) or Synchronization Supply Unit ( SSU ). Two independent jitter attenuating analog PLLs (APLLs) are also integrated; these APLLs generate clocks with jitter below 0.3 ps RMS over the 10 kHz to 20 MHz integration range and can be used to directly time 10GbE or 40GbE network PHYs. The DPLLs lock to a wide variety of telecom and Ethernet reference frequencies and suppress incoming timing faults to generate highly-reliable output clocks for optimal network performance. The T0 DPLL can lock directly to a one pulse per second (1 PPS ) reference enabling the host system to use a low-cost GPS receiver for synchronization. IDT 82V3910 offers a solution optimized for use in Ethernet switches, routers, multiservice switching platforms, wireless backhaul equipment and other communications infrastructure. IDT 82V3910 is available in a 196-ball 15 x 15 mm CABGA package and supports standard industrial temperature range from -40degC to +85degC.
Datasheet

Suppliers

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Synchronous Ethernet SETS for 10GbE and 40GbE - 82V3910AUG8 - Integrated Device Technology
San Jose, CA, USA
Synchronous Ethernet SETS for 10GbE and 40GbE
82V3910AUG8
Synchronous Ethernet SETS for 10GbE and 40GbE 82V3910AUG8
IDT 82V3910 is a single chip synchronous equipment timing source ( SETS ) for synchronous Ethernet (SyncE). The 82V3910 complies with ITU -T G.8262 for EEC -Options 1 and 2; and G.813 for SEC -Options 1 and 2; and it is suitable for SyncE, SONET and SDH equipment. Its ultra-low jitter generation makes it particularly suitable for single-board systems where the SETS directly times 10GBASE -R, 10GBASE -W, OC -192/ STM -64 or 40GBASE -R PHYs. The high-integration architecture minimizes component count and board space by including a “T0” G.8262 compliant digital PLL ( DPLL ); and a “T4” rate converting DPLL to provide recovered line timing to a local Building Integrated Timing Supply ( BITS ) or Synchronization Supply Unit ( SSU ). Two independent jitter attenuating analog PLLs (APLLs) are also integrated; these APLLs generate clocks with jitter below 0.3 ps RMS over the 10 kHz to 20 MHz integration range and can be used to directly time 10GbE or 40GbE network PHYs. The DPLLs lock to a wide variety of telecom and Ethernet reference frequencies and suppress incoming timing faults to generate highly-reliable output clocks for optimal network performance. The T0 DPLL can lock directly to a one pulse per second (1 PPS ) reference enabling the host system to use a low-cost GPS receiver for synchronization. IDT 82V3910 offers a solution optimized for use in Ethernet switches, routers, multiservice switching platforms, wireless backhaul equipment and other communications infrastructure. IDT 82V3910 is available in a 196-ball 15 x 15 mm CABGA package and supports standard industrial temperature range from -40degC to +85degC.

IDT 82V3910 is a single chip synchronous equipment timing source ( SETS ) for synchronous Ethernet (SyncE). The 82V3910 complies with ITU -T G.8262 for EEC -Options 1 and 2; and G.813 for SEC -Options 1 and 2; and it is suitable for SyncE, SONET and SDH equipment. Its ultra-low jitter generation makes it particularly suitable for single-board systems where the SETS directly times 10GBASE -R, 10GBASE -W, OC -192/ STM -64 or 40GBASE -R PHYs.
The high-integration architecture minimizes component count and board space by including a “T0” G.8262 compliant digital PLL ( DPLL ); and a “T4” rate converting DPLL to provide recovered line timing to a local Building Integrated Timing Supply ( BITS ) or Synchronization Supply Unit ( SSU ). Two independent jitter attenuating analog PLLs (APLLs) are also integrated; these APLLs generate clocks with jitter below 0.3 ps RMS over the 10 kHz to 20 MHz integration range and can be used to directly time 10GbE or 40GbE network PHYs. The DPLLs lock to a wide variety of telecom and Ethernet reference frequencies and suppress incoming timing faults to generate highly-reliable output clocks for optimal network performance. The T0 DPLL can lock directly to a one pulse per second (1 PPS ) reference enabling the host system to use a low-cost GPS receiver for synchronization.
IDT 82V3910 offers a solution optimized for use in Ethernet switches, routers, multiservice switching platforms, wireless backhaul equipment and other communications infrastructure. IDT 82V3910 is available in a 196-ball 15 x 15 mm CABGA package and supports standard industrial temperature range from -40degC to +85degC.

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Technical Specifications

  Integrated Device Technology
Product Category IC Timers
Product Number 82V3910AUG8
Product Name Synchronous Ethernet SETS for 10GbE and 40GbE
Bus Interface LVPECL; LVDS; LVPECL,LVDS,LVCMOS
Package Type Surface Mount; CABGA
Supply Voltage 3.3 volts
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