Description
Features:
e500 core running 533 or 833 MHz with :
L1 caches : 32KB Inst. and 32KB Data with parity
256 KB of L2 integrated cache or private SRAM
MMU and FPU-SP capabilities
DMA-channel controllers
128 or 256MB SDRAM-DDR266
16-64 MB soldered Flash
32KB SPI EEPROM
2KB I2C EPROM
PPC Real Time clock and four 32 bit-timers
Calendar clock with lithium cell or supercap backup.
An integrated security engine that supports DES, 3DES, MD-5, SHA-1, AES, ARC4 and other encryption algorithms
A USB 2.0 Full / low speed host or device (8757 only)
Extended temp versions
