The WM8960 is a low power stereo codec featuring Class D speaker drivers to provide 1 W per channel into 8 W loads. Guaranteed low leakage, excellent PSRR and pop/click suppression mechanisms enable direct battery connection for the speaker supply. This IC integrates a complete microphone interface and a stereo headphone driver. External component requirements are drastically reduced as no separate microphone, speaker or headphone amplifiers are required. Advanced on-chip digital signal processing performs automatic level control for the microphone or line input. Stereo 24-bit Delta Sigma converters are used with low power over-sampling digital interpolation and decimation filters and a flexible digital audio interface. The master clock can be input directly or generated internally by an onboard PLL, supporting most commonly used clocking schemes.
Features
DAC SNR 98 dB (’A’ weighted), THD -84 dB at 48 kHz, 3.3V
ADC SNR 95 dB (’A’ weighted),THD -82 dB at 48 kHz, 3.3V
Pop and click suppression
Microphone interface
Programmable ALC / limiter and noise gate
3D stereo enhancement
Stereo class D speaker driver
1W per channel into 8ω BTL speakers
Flexible switching clock
Filterless connection supported
On-chip headphone driver 40mW output power into 16ω at 3.3V
Capless mode
Low power consumption
10mW headphone playback (2.7V / 1.8V supplies)
20mW record and playback (2.7V / 1.8V supplies)
Low supply voltages
Analog 2.7V to 3.6V (AVDD)
Speaker 2.7V to 5.5V (SPKVDD)
Digital core: 1.71V to 3.6V (DCVDD)
Digital I/O: 1.71V to 3.6V (DBVDD)
On-chip PLL provides flexible clocking scheme
Sample rates: 8, 11.025, 12, 16, 22.05, 24, 32, 44.1, 48
5x5x0.9mm 32-pin QFN package
The WM8960 is a low power stereo codec featuring Class D speaker drivers to provide 1 W per channel into 8 W loads. Guaranteed low leakage, excellent PSRR and pop/click suppression mechanisms enable direct battery connection for the speaker supply. This IC integrates a complete microphone interface and a stereo headphone driver. External component requirements are drastically reduced as no separate microphone, speaker or headphone amplifiers are required. Advanced on-chip digital signal processing performs automatic level control for the microphone or line input. Stereo 24-bit Delta Sigma converters are used with low power over-sampling digital interpolation and decimation filters and a flexible digital audio interface. The master clock can be input directly or generated internally by an onboard PLL, supporting most commonly used clocking schemes.
Features
- DAC SNR 98 dB (’A’ weighted), THD -84 dB at 48 kHz, 3.3V
- ADC SNR 95 dB (’A’ weighted),THD -82 dB at 48 kHz, 3.3V
- Pop and click suppression
- Microphone interface
- Programmable ALC / limiter and noise gate
- 3D stereo enhancement
- Stereo class D speaker driver
- 1W per channel into 8Ω BTL speakers
- Flexible switching clock
- Filterless connection supported
- On-chip headphone driver 40mW output power into 16Ω at 3.3V
- Capless mode
- Low power consumption
- 10mW headphone playback (2.7V / 1.8V supplies)
- 20mW record and playback (2.7V / 1.8V supplies)
- Low supply voltages
- Analog 2.7V to 3.6V (AVDD)
- Speaker 2.7V to 5.5V (SPKVDD)
- Digital core: 1.71V to 3.6V (DCVDD)
- Digital I/O: 1.71V to 3.6V (DBVDD)
- On-chip PLL provides flexible clocking scheme
- Sample rates: 8, 11.025, 12, 16, 22.05, 24, 32, 44.1, 48
- 5x5x0.9mm 32-pin QFN package
