The WM8782 is a high performance, low cost stereo audio ADC designed for recordable media applications. The device offers stereo line level inputs along with two control input pins (FORMAT, IWL) to allow operation of the audio interface in three industry standard modes. An internal op-amp is integrated on the front end of the chip to accommodate analog input signals greater than 1Vrms. The device also has a high pass filter to remove residual DC offsets. WM8782 offers Master or Slave mode clocking schemes. A control input pin M/S is used to allow Slave mode operation or Master mode operation. A stereo 24-bit multi-bit Delta Sigma ADC is used with 128x, 64x or 32x over-sampling, according to sample rate. Digital audio output word lengths from 16-24 bits and sampling rates from 8 kHz to 192 kHz are supported. The device is a hardware controlled device and is supplied in a 20-lead SSOP or 20-lead TSSOP package.
Features
Master or slave clocking mode
System clock (MCLK): 128fs, 192fs, 256fs, 384fs, 512fs, 768fs
Audio data interface modes
16-24 bit I²S, 16-24 bit left, 16-24 bit right justified
The WM8782 is a high performance, low cost stereo audio ADC designed for recordable media applications. The device offers stereo line level inputs along with two control input pins (FORMAT, IWL) to allow operation of the audio interface in three industry standard modes. An internal op-amp is integrated on the front end of the chip to accommodate analog input signals greater than 1Vrms. The device also has a high pass filter to remove residual DC offsets. WM8782 offers Master or Slave mode clocking schemes. A control input pin M/S is used to allow Slave mode operation or Master mode operation. A stereo 24-bit multi-bit Delta Sigma ADC is used with 128x, 64x or 32x over-sampling, according to sample rate. Digital audio output word lengths from 16-24 bits and sampling rates from 8 kHz to 192 kHz are supported. The device is a hardware controlled device and is supplied in a 20-lead SSOP or 20-lead TSSOP package.
Features
- Master or slave clocking mode
- System clock (MCLK): 128fs, 192fs, 256fs, 384fs, 512fs, 768fs
- Audio data interface modes
- 16-24 bit I²S, 16-24 bit left, 16-24 bit right justified
