Nexperia B.V. Octal D-type transparent latch; 3-state 74HCT573PW,118

Description
The 74HC573; 74HCT573 is an 8-bit D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of LE. A HIGH on OEcauses the outputs to assume a high-impedance OFF-state. Operation of the OEinput does not affect the state of the latches. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. Features and benefits Wide supply voltage range from 2.0 V to 6.0 V CMOS low power dissipation High noise immunity Input levels: For 74HC573: CMOS level For 74HCT573: TTL level Inputs and outputs on opposite sides of package allowing easy interface with microprocessors Useful as input or output port for microprocessors and microcomputers 3-state non-inverting outputs for bus-oriented applications Common 3-state output enable input Latch-up performance exceeds 100 mA per JESD 78 Class II Level B Complies with JEDEC standards: JESD8C (2.7 V to 3.6 V) JESD7A (2.0 V to 6.0 V) ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V Multiple package options Specified from -40 °C to +85 °C and from -40 °C to +125 °C
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Description
The 74HC573; 74HCT573 is an 8-bit D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of LE. A HIGH on OEcauses the outputs to assume a high-impedance OFF-state. Operation of the OEinput does not affect the state of the latches. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. Features and benefits Wide supply voltage range from 2.0 V to 6.0 V CMOS low power dissipation High noise immunity Input levels: For 74HC573: CMOS level For 74HCT573: TTL level Inputs and outputs on opposite sides of package allowing easy interface with microprocessors Useful as input or output port for microprocessors and microcomputers 3-state non-inverting outputs for bus-oriented applications Common 3-state output enable input Latch-up performance exceeds 100 mA per JESD 78 Class II Level B Complies with JEDEC standards: JESD8C (2.7 V to 3.6 V) JESD7A (2.0 V to 6.0 V) ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V Multiple package options Specified from -40 °C to +85 °C and from -40 °C to +125 °C
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Octal D-type transparent latch; 3-state - 74HCT573PW,118 - Nexperia B.V.
Nijmegen, Netherlands
Octal D-type transparent latch; 3-state
74HCT573PW,118
Octal D-type transparent latch; 3-state 74HCT573PW,118
The 74HC573; 74HCT573 is an 8-bit D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of LE. A HIGH on OEcauses the outputs to assume a high-impedance OFF-state. Operation of the OEinput does not affect the state of the latches. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. Features and benefits Wide supply voltage range from 2.0 V to 6.0 V CMOS low power dissipation High noise immunity Input levels: For 74HC573: CMOS level For 74HCT573: TTL level Inputs and outputs on opposite sides of package allowing easy interface with microprocessors Useful as input or output port for microprocessors and microcomputers 3-state non-inverting outputs for bus-oriented applications Common 3-state output enable input Latch-up performance exceeds 100 mA per JESD 78 Class II Level B Complies with JEDEC standards: JESD8C (2.7 V to 3.6 V) JESD7A (2.0 V to 6.0 V) ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V Multiple package options Specified from -40 °C to +85 °C and from -40 °C to +125 °C

The 74HC573; 74HCT573 is an 8-bit D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of LE. A HIGH on OEcauses the outputs to assume a high-impedance OFF-state. Operation of the OEinput does not affect the state of the latches. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

Features and benefits

  • Wide supply voltage range from 2.0 V to 6.0 V
  • CMOS low power dissipation
  • High noise immunity
  • Input levels:
    • For 74HC573: CMOS level
    • For 74HCT573: TTL level
  • Inputs and outputs on opposite sides of package allowing easy interface with microprocessors
  • Useful as input or output port for microprocessors and microcomputers
  • 3-state non-inverting outputs for bus-oriented applications
  • Common 3-state output enable input
  • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
  • Complies with JEDEC standards:
    • JESD8C (2.7 V to 3.6 V)
    • JESD7A (2.0 V to 6.0 V)
  • ESD protection:
    • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
  • Multiple package options
  • Specified from -40 °C to +85 °C and from -40 °C to +125 °C
Supplier's Site Datasheet
Laguna Hills, CA, United States
Logic - Logic - Latches - 74HCT573PW,118
1008831-74HCT573PW,118
Logic - Logic - Latches - 74HCT573PW,118 1008831-74HCT573PW,118
Manufacturer: Nexperia USA Inc. Win Source Part Number: 1008831-74HCT573PW,1 18 Packaging: Reel - TR Mounting: SMD (SMT) Logic Type: D-Type Transparent Latch Output Type: Tri-State Current - Output High, Low: 6mA, 6mA Independent Circuits: 1 Categories: Integrated Circuits Status: Active Temperature Range - Operating: -40°C to 125°C Case / Package: 20-TSSOP Supply Voltage - Operating: 4.5 V to 5.5 V Propagation Delay Time (ns): 17ns Popularity: Medium Fake Threat In the Open Market: 42 pct. Supply and Demand Status: Balance

Manufacturer: Nexperia USA Inc.
Win Source Part Number: 1008831-74HCT573PW,118
Packaging: Reel - TR
Mounting: SMD (SMT)
Logic Type: D-Type Transparent Latch
Output Type: Tri-State
Current - Output High, Low: 6mA, 6mA
Independent Circuits: 1
Categories: Integrated Circuits
Status: Active
Temperature Range - Operating: -40°C to 125°C
Case / Package: 20-TSSOP
Supply Voltage - Operating: 4.5 V to 5.5 V
Propagation Delay Time (ns): 17ns
Popularity: Medium
Fake Threat In the Open Market: 42 pct.
Supply and Demand Status: Balance

Buy Now Datasheet
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D-Type Transparent Latch 1 Channel 8:8 IC Tri-State 20-TSSOP

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D-Type Transparent Latch 1 Channel 8:8 IC Tri-State 20-TSSOP

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Latches - 74HCT573PW,118 - Quarktwin Technology Ltd.
Shenzhen, Guangdong, China
D-Type Transparent Latch 1 Channel 8:8 IC Tri-State 20-TSSOP

D-Type Transparent Latch 1 Channel 8:8 IC Tri-State 20-TSSOP

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Integrated Circuits (ICs) - Logic - Latches - 74HCT573PW,118 - Shenzhen Shengyu Electronics Technology Limited
Futian, China
Integrated Circuits (ICs) - Logic - Latches
74HCT573PW,118
Integrated Circuits (ICs) - Logic - Latches 74HCT573PW,118
IC D-TYPE TRANSP SGL 8:8 20TSSOP

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Supplier's Site
Futian, Shenzhen, China
Logic ICs >> Latches
74HCT573PW,118
Logic ICs >> Latches 74HCT573PW,118
4.5V~5.5V D-Typelocking Latch TSSOP-20 Latches ROHS

4.5V~5.5V D-Typelocking Latch TSSOP-20 Latches ROHS

Supplier's Site Datasheet
Logic - Latches - 74HCT573PW,118 - Lingto Electronic Limited
Shenzhen, China
Logic - Latches
74HCT573PW,118
Logic - Latches 74HCT573PW,118
IC OCTAL D TRANSP LATCH 20TSSOP

IC OCTAL D TRANSP LATCH 20TSSOP

Supplier's Site Datasheet
Latch, D Type Transp, 3-State, Tssop-20; Logic Family / Base Number Nexperia - 85X2852 - Newark, An Avnet Company
Chicago, IL, United States
Latch, D Type Transp, 3-State, Tssop-20; Logic Family / Base Number Nexperia
85X2852
Latch, D Type Transp, 3-State, Tssop-20; Logic Family / Base Number Nexperia 85X2852
LATCH, D TYPE TRANSP, 3-STATE, TSSOP-20; Logic Family / Base Number:74HCT573; Latch Type:D Type Transparent; IC Output Type:Tri State Non Inverted; Propagation Delay:-; Output Current:35mA; Logic Case Style:TSSOP; No. of Pins:20Pins;RoHS Compliant: Yes

LATCH, D TYPE TRANSP, 3-STATE, TSSOP-20; Logic Family / Base Number:74HCT573; Latch Type:D Type Transparent; IC Output Type:Tri State Non Inverted; Propagation Delay:-; Output Current:35mA; Logic Case Style:TSSOP; No. of Pins:20Pins;RoHS Compliant: Yes

Supplier's Site Datasheet
D-Latch, Transparent, Octal, Tssop-20; Logic Family / Base Number Nexperia - 93X4841 - Newark, An Avnet Company
Chicago, IL, United States
D-Latch, Transparent, Octal, Tssop-20; Logic Family / Base Number Nexperia
93X4841
D-Latch, Transparent, Octal, Tssop-20; Logic Family / Base Number Nexperia 93X4841
D-LATCH, TRANSPARENT, OCTAL, TSSOP-20; Logic Family / Base Number:74HCT573; Latch Type:D Type Transparent; IC Output Type:Tri State Non Inverted; Propagation Delay:-; Output Current:35mA; Logic Case Style:TSSOP; No. of Pins:20Pins; RoHS Compliant: Yes

D-LATCH, TRANSPARENT, OCTAL, TSSOP-20; Logic Family / Base Number:74HCT573; Latch Type:D Type Transparent; IC Output Type:Tri State Non Inverted; Propagation Delay:-; Output Current:35mA; Logic Case Style:TSSOP; No. of Pins:20Pins; RoHS Compliant: Yes

Supplier's Site Datasheet

Technical Specifications

  Nexperia B.V. Win Source Electronics DigiKey Quarktwin Technology Ltd. Shenzhen Shengyu Electronics Technology Limited LCSC Electronics Technology (HK) Limited Lingto Electronic Limited Newark, An Avnet Company
Product Category Logic Latches Logic Latches Logic Latches Logic Latches Logic Latches Logic Latches Logic Latches Logic Latches
Product Number 74HCT573PW,118 1008831-74HCT573PW,118 1727-6358-1-ND 74HCT573PW,118 74HCT573PW,118 74HCT573PW,118 74HCT573PW,118 85X2852
Product Name Octal D-type transparent latch; 3-state Logic - Logic - Latches - 74HCT573PW,118 Latches Latches Integrated Circuits (ICs) - Logic - Latches Logic ICs >> Latches Logic - Latches Latch, D Type Transp, 3-State, Tssop-20; Logic Family / Base Number Nexperia
Latch Type Transparent-D Transparent-D D-Typelocking Latch D; Transparent-D
Output Characteristics 3-State 3-State Tri-State
Features ESD Protection
Supply Voltage +7 4.5 V ~ 5.5 V 4.5V ~ 5.5V 4.5V ~ 5.5V 4.5V~5.5V
Package Type SOT360-1 SOT360-1 TSSOP; 20-TSSOP; SOP; SSOP TSSOP; "20-TSSOP (0.173"", 4.40mm Width)" TSSOP; 20-TSSOP (0.173\", 4.40mm Width); SOP; SSOP SSOP TSSOP; SSOP TSSOP; TSSOP
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