Nexperia B.V. Dual JK flip-flop with set and reset; negative-edge trigger 74HCT112PW,118

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Dual JK flip-flop with set and reset; negative-edge trigger - 74HCT112PW,118 - Nexperia B.V.
Nijmegen, Netherlands
Dual JK flip-flop with set and reset; negative-edge trigger
74HCT112PW,118
Dual JK flip-flop with set and reset; negative-edge trigger 74HCT112PW,118
The 74HC112; 74HCT112 is a dual negative-edge triggered JK flip-flop. It features individual J and K inputs, clock (nCP) set (nSD) and reset (nRD) inputs. It also has complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. The J and K inputs control the state changes of the flip-flops as described in the mode select function table. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. Features and benefits Input levels: For 74HC112: CMOS level For 74HCT112: TTL level Asynchronous set and reset Specified in compliance with JEDEC standard no. 7A ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Specified from -40 °C to +85 °C and from -40 °C to +125 °C

The 74HC112; 74HCT112 is a dual negative-edge triggered JK flip-flop. It features individual J and K inputs, clock (nCP) set (nSD) and reset (nRD) inputs. It also has complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. The J and K inputs control the state changes of the flip-flops as described in the mode select function table. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC.

Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.

Features and benefits

  • Input levels:
    • For 74HC112: CMOS level
    • For 74HCT112: TTL level
  • Asynchronous set and reset
  • Specified in compliance with JEDEC standard no. 7A
  • ESD protection:
    • HBM JESD22-A114F exceeds 2000 V
    • MM JESD22-A115-A exceeds 200 V
  • Specified from -40 °C to +85 °C and from -40 °C to +125 °C
Supplier's Site Datasheet
Yishun, Singapore
Logic - Logic - Flip Flops - 74HCT112PW,118
1008593-74HCT112PW,118
Logic - Logic - Flip Flops - 74HCT112PW,118 1008593-74HCT112PW,118
Manufacturer: Nexperia USA Inc. Win Source Part Number: 1008593-74HCT112PW,1 18 Packaging: Reel - TR Type: JK Type Mounting: SMD (SMT) Output Type: Differential Current - Output High, Low: 4mA, 4mA Number of Elements: 2 Number of Bits per Element: 1 Max Propagation Delay @ V, Max CL: 35ns @ 4.5V, 50pF Trigger Type: Negative Edge Current - Quiescent: 4μA Input Capacitance: 3.5pF Categories: Integrated Circuits Status: Active Temperature Range - Operating: -40°C to 125°C (TA) Dimension: 16-TSSOP (0.173", 4.40mm Width) Purpose: Set(Preset) and Reset Supply Voltage - Operating: 4.5 V to 5.5 V Max Frequency: 64MHz Popularity: Medium Fake Threat In the Open Market: 65 pct. Supply and Demand Status: Balance

Manufacturer: Nexperia USA Inc.
Win Source Part Number: 1008593-74HCT112PW,118
Packaging: Reel - TR
Type: JK Type
Mounting: SMD (SMT)
Output Type: Differential
Current - Output High, Low: 4mA, 4mA
Number of Elements: 2
Number of Bits per Element: 1
Max Propagation Delay @ V, Max CL: 35ns @ 4.5V, 50pF
Trigger Type: Negative Edge
Current - Quiescent: 4μA
Input Capacitance: 3.5pF
Categories: Integrated Circuits
Status: Active
Temperature Range - Operating: -40°C to 125°C (TA)
Dimension: 16-TSSOP (0.173", 4.40mm Width)
Purpose: Set(Preset) and Reset
Supply Voltage - Operating: 4.5 V to 5.5 V
Max Frequency: 64MHz
Popularity: Medium
Fake Threat In the Open Market: 65 pct.
Supply and Demand Status: Balance

Supplier's Site Datasheet
Logic - Flip Flops - 74HCT112PW,118 - Lingto Electronic Limited
Shenzhen, China
Logic - Flip Flops
74HCT112PW,118
Logic - Flip Flops 74HCT112PW,118
IC FF JK TYPE DUAL 1BIT 16TSSOP

IC FF JK TYPE DUAL 1BIT 16TSSOP

Supplier's Site Datasheet
Logic - Flip Flops -  - Nova Technology(HK) Co.,Ltd
Futian District, Shenzhen, China
Logic - Flip Flops
Logic - Flip Flops
Flip Flop 2 Element JK Type 1 Bit Negative Edge 16-TSSOP (0.173

Flip Flop 2 Element JK Type 1 Bit Negative Edge 16-TSSOP (0.173

Supplier's Site Datasheet
Flip Flops - 1727-74HCT112PW,118TR-ND - DigiKey
Thief River Falls, MN, United States
IC FF JK TYPE DUAL 1BIT 16TSSOP

IC FF JK TYPE DUAL 1BIT 16TSSOP

Supplier's Site Datasheet

Technical Specifications

  Nexperia B.V. Win Source Electronics Lingto Electronic Limited Nova Technology(HK) Co.,Ltd DigiKey
Product Category Flip-Flops Flip-Flops Flip-Flops Flip-Flops Flip-Flops
Product Number 74HCT112PW,118 1008593-74HCT112PW,118 74HCT112PW,118 1727-74HCT112PW,118TR-ND
Product Name Dual JK flip-flop with set and reset; negative-edge trigger Logic - Logic - Flip Flops - 74HCT112PW,118 Logic - Flip Flops Logic - Flip Flops Flip Flops
Flip-Flop Type J-K J-K J-K
Triggering Negative-edge Triggered Negative-edge Triggered; Negative Edge Negative-edge Triggered Negative-edge Triggered
Supply Voltage 5V; 4.5 - 5.5 4.5 V ~ 5.5 V 4.5V ~ 5.5V
Features ESD Protection
Propagation Delay 19 ns 35 ns 35 ns
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