Nexperia B.V. Octal D-type flip-flop with reset; positive-edge trigger 74HC273PW,112

Description
The 74HC273; 74HCT273 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A LOW on MR forces the outputs LOW independently of clock and data inputs. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. Features and benefits Wide supply voltage range from 2.0 V to 6.0 V CMOS low power dissipation High noise immunity Latch-up performance exceeds 100 mA per JESD 78 Class II Level B Complies with JEDEC standards: JESD8C (2.7 V to 3.6 V) JESD7A (2.0 V to 6.0 V) Input levels: For 74HC273: CMOS level For 74HCT273: TTL level Common clock and master reset Eight positive edge-triggered D-type flip-flops ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V Multiple package options Specified from -40 °C to +85 °C and from -40 °C to +125 °C
  • Octal D-type flip-flop with reset; positive-edge trigger - 74HC273PW,112 - Nexperia B.V.
    Nexperia B.V.
  • Flip Flops - 74HC273PW,112-ND - DigiKey
    DigiKey
  • 74HC273PW,112 - Rochester Electronics
    Rochester Electronics
  • Logic - Flip Flops - 74HC273PW,112 - Lingto Electronic Limited
    Lingto Electronic Limited
  • Flip Flops - 74HC273PW,112 - Quarktwin Technology Ltd.
    Quarktwin Technology Ltd.
  • Integrated Circuits (ICs) - Logic - Flip Flops - 74HC273PW,112 - Shenzhen Shengyu Electronics Technology Limited
    Shenzhen Shengyu Electronics Technology Limited
Request a Quote Datasheet
Description
The 74HC273; 74HCT273 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A LOW on MR forces the outputs LOW independently of clock and data inputs. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. Features and benefits Wide supply voltage range from 2.0 V to 6.0 V CMOS low power dissipation High noise immunity Latch-up performance exceeds 100 mA per JESD 78 Class II Level B Complies with JEDEC standards: JESD8C (2.7 V to 3.6 V) JESD7A (2.0 V to 6.0 V) Input levels: For 74HC273: CMOS level For 74HCT273: TTL level Common clock and master reset Eight positive edge-triggered D-type flip-flops ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V Multiple package options Specified from -40 °C to +85 °C and from -40 °C to +125 °C
Request a Quote Datasheet

Suppliers

Company
Product
Description
Supplier Links
Octal D-type flip-flop with reset; positive-edge trigger - 74HC273PW,112 - Nexperia B.V.
Nexperia B.V.
Nijmegen, Netherlands
Octal D-type flip-flop with reset; positive-edge trigger
74HC273PW,112
Octal D-type flip-flop with reset; positive-edge trigger 74HC273PW,112
The 74HC273; 74HCT273 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A LOW on MR forces the outputs LOW independently of clock and data inputs. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. Features and benefits Wide supply voltage range from 2.0 V to 6.0 V CMOS low power dissipation High noise immunity Latch-up performance exceeds 100 mA per JESD 78 Class II Level B Complies with JEDEC standards: JESD8C (2.7 V to 3.6 V) JESD7A (2.0 V to 6.0 V) Input levels: For 74HC273: CMOS level For 74HCT273: TTL level Common clock and master reset Eight positive edge-triggered D-type flip-flops ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V Multiple package options Specified from -40 °C to +85 °C and from -40 °C to +125 °C

The 74HC273; 74HCT273 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A LOW on MR forces the outputs LOW independently of clock and data inputs. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

Features and benefits

  • Wide supply voltage range from 2.0 V to 6.0 V
  • CMOS low power dissipation
  • High noise immunity
  • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
  • Complies with JEDEC standards:
    • JESD8C (2.7 V to 3.6 V)
    • JESD7A (2.0 V to 6.0 V)
  • Input levels:
    • For 74HC273: CMOS level
    • For 74HCT273: TTL level
  • Common clock and master reset
  • Eight positive edge-triggered D-type flip-flops
  • ESD protection:
    • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
  • Multiple package options
  • Specified from -40 °C to +85 °C and from -40 °C to +125 °C
Supplier's Site Datasheet
Flip Flops - 74HC273PW,112-ND - DigiKey
DigiKey
Thief River Falls, MN, United States
Flip Flops
74HC273PW,112-ND
Flip Flops 74HC273PW,112-ND
"Flip Flop 1 Element D-Type 8 Bit Positive Edge 20-TSSOP (0.173"", 4.40mm Width)"

"Flip Flop 1 Element D-Type 8 Bit Positive Edge 20-TSSOP (0.173"", 4.40mm Width)"

Buy Now Datasheet
- 74HC273PW,112 - Rochester Electronics
Rochester Electronics
Newburyport, MA, United States
74HC273PW,112
74HC273PW,112
D Flip-Flop, HC/UH Series, 1-Func, Positive Edge Triggered, 8-Bit, True Output, CMOS, PDSO20

D Flip-Flop, HC/UH Series, 1-Func, Positive Edge Triggered, 8-Bit, True Output, CMOS, PDSO20

Supplier's Site Datasheet
Logic - Flip Flops - 74HC273PW,112 - Lingto Electronic Limited
Lingto Electronic Limited
Shenzhen, China
Logic - Flip Flops
74HC273PW,112
Logic - Flip Flops 74HC273PW,112
IC FF D-TYPE SNGL 8BIT 20TSSOP

IC FF D-TYPE SNGL 8BIT 20TSSOP

Supplier's Site Datasheet
Flip Flops - 74HC273PW,112 - Quarktwin Technology Ltd.
Quarktwin Technology Ltd.
Shenzhen, Guangdong, China
Flip Flops
74HC273PW,112
Flip Flops 74HC273PW,112
Flip Flop 1 Element D-Type 8 Bit Positive Edge 20-TSSOP (0.173", 4.40mm Width)

Flip Flop 1 Element D-Type 8 Bit Positive Edge 20-TSSOP (0.173", 4.40mm Width)

Buy Now Datasheet
Integrated Circuits (ICs) - Logic - Flip Flops - 74HC273PW,112 - Shenzhen Shengyu Electronics Technology Limited
Shenzhen Shengyu Electronics Technology Limited
Futian, China
Integrated Circuits (ICs) - Logic - Flip Flops
74HC273PW,112
Integrated Circuits (ICs) - Logic - Flip Flops 74HC273PW,112
IC FF D-TYPE SNGL 8BIT 20TSSOP

IC FF D-TYPE SNGL 8BIT 20TSSOP

Supplier's Site

Technical Specifications

  Nexperia B.V. DigiKey Rochester Electronics Lingto Electronic Limited Quarktwin Technology Ltd. Shenzhen Shengyu Electronics Technology Limited
Product Category Flip-Flops Flip-Flops Flip-Flops Flip-Flops Flip-Flops Flip-Flops
Product Number 74HC273PW,112 74HC273PW,112-ND 74HC273PW,112 74HC273PW,112 74HC273PW,112 74HC273PW,112
Product Name Octal D-type flip-flop with reset; positive-edge trigger Flip Flops Logic - Flip Flops Flip Flops Integrated Circuits (ICs) - Logic - Flip Flops
Flip-Flop Type D D D
Triggering Positive-edge Triggered Positive-edge Triggered Positive-edge Triggered
Supply Voltage 2.5V; 3V; 3.3V; 3.6V; 5V; 2.0 - 6.0 2V ~ 6V 2V ~ 6V
Features ESD Protection
Propagation Delay 15 ns 26 ns
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