Nexperia B.V. Dual JK flip-flop with set and reset; negative-edge trigger 74HC112D,653

The 74HC112; 74HCT112 is a dual negative-edge triggered JK flip-flop. It features individual J and K inputs, clock (nCP) set (nSD) and reset (nRD) inputs. It also has complementary nQ and nQoutputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. The J and K inputs control the state changes of the flip-flops as described in the mode select function table. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of V_CC.

Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.

Features and benefits

• Input levels:
• For 74HC112: CMOS level
• For 74HCT112: TTL level
• Asynchronous set and reset
• Specified in compliance with JEDEC standard no. 7A
• ESD protection:
• HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
• CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
• Specified from -40 °C to +85 °C and from -40 °C to +125 °C

J-K Flip-Flop, HC/UH Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, CMOS, PDSO16

"Flip Flop 2 Element JK Type 1 Bit Negative Edge 16-SOIC (0.154"", 3.90mm Width)"

"Flip Flop 2 Element JK Type 1 Bit Negative Edge 16-SOIC (0.154"", 3.90mm Width)"

"Flip Flop 2 Element JK Type 1 Bit Negative Edge 16-SOIC (0.154"", 3.90mm Width)"