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Nexperia B.V. Dual JK flip-flop with set and reset; negative-edge trigger 74HC112D,653

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Dual JK flip-flop with set and reset; negative-edge trigger - 74HC112D,653 - Nexperia B.V.
Nijmegen, Netherlands
Dual JK flip-flop with set and reset; negative-edge trigger
74HC112D,653
Dual JK flip-flop with set and reset; negative-edge trigger 74HC112D,653
The 74HC112; 74HCT112 is a dual negative-edge triggered JK flip-flop. It features individual J and K inputs, clock (nCP) set (nSD) and reset (nRD) inputs. It also has complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. The J and K inputs control the state changes of the flip-flops as described in the mode select function table. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. Features and benefits Input levels: For 74HC112: CMOS level For 74HCT112: TTL level Asynchronous set and reset Specified in compliance with JEDEC standard no. 7A ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V Specified from -40 °C to +85 °C and from -40 °C to +125 °C

The 74HC112; 74HCT112 is a dual negative-edge triggered JK flip-flop. It features individual J and K inputs, clock (nCP) set (nSD) and reset (nRD) inputs. It also has complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. The J and K inputs control the state changes of the flip-flops as described in the mode select function table. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC.

Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.

Features and benefits

  • Input levels:
    • For 74HC112: CMOS level
    • For 74HCT112: TTL level
  • Asynchronous set and reset
  • Specified in compliance with JEDEC standard no. 7A
  • ESD protection:
    • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
  • Specified from -40 °C to +85 °C and from -40 °C to +125 °C
Supplier's Site Datasheet
Flip Flops - 74HC112D,653 - Quarktwin Technology Ltd.
Shenzhen, Guangdong, China
Flip Flops
74HC112D,653
Flip Flops 74HC112D,653
Flip Flop 2 Element JK Type 1 Bit Negative Edge 16-SOIC (0.154", 3.90mm Width)

Flip Flop 2 Element JK Type 1 Bit Negative Edge 16-SOIC (0.154", 3.90mm Width)

Supplier's Site Datasheet
Logic - Flip Flops - 74HC112D,653 - Lingto Electronic Limited
Shenzhen, China
Logic - Flip Flops
74HC112D,653
Logic - Flip Flops 74HC112D,653
IC FF JK TYPE DUAL 1BIT 16SO

IC FF JK TYPE DUAL 1BIT 16SO

Supplier's Site Datasheet
Integrated Circuits (ICs) - Logic - Flip Flops - 74HC112D,653 - Shenzhen Shengyu Electronics Technology Limited
Futian, China
Integrated Circuits (ICs) - Logic - Flip Flops
74HC112D,653
Integrated Circuits (ICs) - Logic - Flip Flops 74HC112D,653
IC FF JK TYPE DUAL 1BIT 16SO

IC FF JK TYPE DUAL 1BIT 16SO

Supplier's Site
 - 74HC112D,653 - Rochester Electronics
Newburyport, MA, United States
Nexperia 74HC112D - J-K Flip-Flop, HC/UH Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, CMOS, PDSO16

Nexperia 74HC112D - J-K Flip-Flop, HC/UH Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, CMOS, PDSO16

Supplier's Site Datasheet
Flip Flops - 1727-6577-6-ND - DigiKey
Thief River Falls, MN, United States
Flip Flops
1727-6577-6-ND
Flip Flops 1727-6577-6-ND
Flip Flop 2 Element JK Type 1 Bit Negative Edge 16-SOIC (0.154", 3.90mm Width)

Flip Flop 2 Element JK Type 1 Bit Negative Edge 16-SOIC (0.154", 3.90mm Width)

Supplier's Site Datasheet
Flip Flops - 1727-6577-1-ND - DigiKey
Thief River Falls, MN, United States
Flip Flops
1727-6577-1-ND
Flip Flops 1727-6577-1-ND
Flip Flop 2 Element JK Type 1 Bit Negative Edge 16-SOIC (0.154", 3.90mm Width)

Flip Flop 2 Element JK Type 1 Bit Negative Edge 16-SOIC (0.154", 3.90mm Width)

Supplier's Site Datasheet
Flip Flops - 1727-6577-2-ND - DigiKey
Thief River Falls, MN, United States
Flip Flops
1727-6577-2-ND
Flip Flops 1727-6577-2-ND
Flip Flop 2 Element JK Type 1 Bit Negative Edge 16-SOIC (0.154", 3.90mm Width)

Flip Flop 2 Element JK Type 1 Bit Negative Edge 16-SOIC (0.154", 3.90mm Width)

Supplier's Site Datasheet

Technical Specifications

  Nexperia B.V. Quarktwin Technology Ltd. Lingto Electronic Limited Shenzhen Shengyu Electronics Technology Limited Rochester Electronics DigiKey
Product Category Flip-Flops Flip-Flops Flip-Flops Flip-Flops Flip-Flops Flip-Flops
Product Number 74HC112D,653 74HC112D,653 74HC112D,653 74HC112D,653 74HC112D,653 1727-6577-6-ND
Product Name Dual JK flip-flop with set and reset; negative-edge trigger Flip Flops Logic - Flip Flops Integrated Circuits (ICs) - Logic - Flip Flops Flip Flops
Flip-Flop Type J-K J-K J-K
Triggering Negative-edge Triggered Negative-edge Triggered Negative-edge Triggered
Supply Voltage 2.5V; 3V; 3.3V; 3.6V; 5V; 2.0 - 6.0 2V ~ 6V 2V ~ 6V
Features ESD Protection
Propagation Delay 15 ns 30 ns
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