Nexperia B.V. Low-power dual D-type flip-flop; positive-edge trigger 74AUP2G80DC,125

Description
The 74AUP2G80 provides the dual positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Qoutput on the LOW-to-HIGH transition of the clock pulse. The input pin D must be stable one setup time prior to the LOW-to-HIGH clock transition for predictable operation. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing a damaging backflow current through the device when it is powered down. Features and benefits Wide supply voltage range from 0.8 V to 3.6 V High noise immunity Low static power consumption; ICC = 0.9 μA (maximum) Latch-up performance exceeds 100 mA per JESD78 Class II Inputs accept voltages up to 3.6 V Low noise overshoot and undershoot < 10 % of VCC IOFF circuitry provides partial Power-down mode operation Complies with JEDEC standards: JESD8-12 (0.8 V to 1.3 V) JESD8-11 (0.9 V to 1.65 V) JESD8-7 (1.2 V to 1.95 V) JESD8-5 (1.8 V to 2.7 V) JESD8-B (2.7 V to 3.6 V) ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V Multiple package options Specified from -40 °C to +85 °C and -40 °C to +125 °C
Request a Quote Datasheet
Description
The 74AUP2G80 provides the dual positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Qoutput on the LOW-to-HIGH transition of the clock pulse. The input pin D must be stable one setup time prior to the LOW-to-HIGH clock transition for predictable operation. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing a damaging backflow current through the device when it is powered down. Features and benefits Wide supply voltage range from 0.8 V to 3.6 V High noise immunity Low static power consumption; ICC = 0.9 μA (maximum) Latch-up performance exceeds 100 mA per JESD78 Class II Inputs accept voltages up to 3.6 V Low noise overshoot and undershoot < 10 % of VCC IOFF circuitry provides partial Power-down mode operation Complies with JEDEC standards: JESD8-12 (0.8 V to 1.3 V) JESD8-11 (0.9 V to 1.65 V) JESD8-7 (1.2 V to 1.95 V) JESD8-5 (1.8 V to 2.7 V) JESD8-B (2.7 V to 3.6 V) ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V Multiple package options Specified from -40 °C to +85 °C and -40 °C to +125 °C
Request a Quote Datasheet

Suppliers

Company
Product
Description
Supplier Links
Low-power dual D-type flip-flop; positive-edge trigger - 74AUP2G80DC,125 - Nexperia B.V.
Nijmegen, Netherlands
Low-power dual D-type flip-flop; positive-edge trigger
74AUP2G80DC,125
Low-power dual D-type flip-flop; positive-edge trigger 74AUP2G80DC,125
The 74AUP2G80 provides the dual positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Qoutput on the LOW-to-HIGH transition of the clock pulse. The input pin D must be stable one setup time prior to the LOW-to-HIGH clock transition for predictable operation. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing a damaging backflow current through the device when it is powered down. Features and benefits Wide supply voltage range from 0.8 V to 3.6 V High noise immunity Low static power consumption; ICC = 0.9 μA (maximum) Latch-up performance exceeds 100 mA per JESD78 Class II Inputs accept voltages up to 3.6 V Low noise overshoot and undershoot < 10 % of VCC IOFF circuitry provides partial Power-down mode operation Complies with JEDEC standards: JESD8-12 (0.8 V to 1.3 V) JESD8-11 (0.9 V to 1.65 V) JESD8-7 (1.2 V to 1.95 V) JESD8-5 (1.8 V to 2.7 V) JESD8-B (2.7 V to 3.6 V) ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V Multiple package options Specified from -40 °C to +85 °C and -40 °C to +125 °C

The 74AUP2G80 provides the dual positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Qoutput on the LOW-to-HIGH transition of the clock pulse. The input pin D must be stable one setup time prior to the LOW-to-HIGH clock transition for predictable operation.

Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.

This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.

This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing a damaging backflow current through the device when it is powered down.

Features and benefits

  • Wide supply voltage range from 0.8 V to 3.6 V
  • High noise immunity
  • Low static power consumption; ICC = 0.9 μA (maximum)
  • Latch-up performance exceeds 100 mA per JESD78 Class II
  • Inputs accept voltages up to 3.6 V
  • Low noise overshoot and undershoot < 10 % of VCC
  • IOFF circuitry provides partial Power-down mode operation
  • Complies with JEDEC standards:
    • JESD8-12 (0.8 V to 1.3 V)
    • JESD8-11 (0.9 V to 1.65 V)
    • JESD8-7 (1.2 V to 1.95 V)
    • JESD8-5 (1.8 V to 2.7 V)
    • JESD8-B (2.7 V to 3.6 V)
  • ESD protection:
    • HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V
    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
  • Multiple package options
  • Specified from -40 °C to +85 °C and -40 °C to +125 °C
Supplier's Site Datasheet
Flip Flops - 1727-7901-1-ND - DigiKey
Thief River Falls, MN, United States
Flip Flops
1727-7901-1-ND
Flip Flops 1727-7901-1-ND
"Flip Flop 2 Element D-Type 1 Bit Positive Edge 8-VFSOP (0.091"", 2.30mm Width)"

"Flip Flop 2 Element D-Type 1 Bit Positive Edge 8-VFSOP (0.091"", 2.30mm Width)"

Buy Now Datasheet
Flip Flops - 1727-7901-2-ND - DigiKey
Thief River Falls, MN, United States
Flip Flops
1727-7901-2-ND
Flip Flops 1727-7901-2-ND
"Flip Flop 2 Element D-Type 1 Bit Positive Edge 8-VFSOP (0.091"", 2.30mm Width)"

"Flip Flop 2 Element D-Type 1 Bit Positive Edge 8-VFSOP (0.091"", 2.30mm Width)"

Buy Now Datasheet
Flip Flops - 1727-7901-6-ND - DigiKey
Thief River Falls, MN, United States
Flip Flops
1727-7901-6-ND
Flip Flops 1727-7901-6-ND
"Flip Flop 2 Element D-Type 1 Bit Positive Edge 8-VFSOP (0.091"", 2.30mm Width)"

"Flip Flop 2 Element D-Type 1 Bit Positive Edge 8-VFSOP (0.091"", 2.30mm Width)"

Buy Now Datasheet
Integrated Circuits (ICs) - Logic - Flip Flops - 1370980-74AUP2G80DC,125 - Win Source Electronics
Laguna Hills, CA, United States
Integrated Circuits (ICs) - Logic - Flip Flops
1370980-74AUP2G80DC,125
Integrated Circuits (ICs) - Logic - Flip Flops 1370980-74AUP2G80DC,125
Win Source Part Number: 1370980-74AUP2G80DC, 125 Category: Integrated Circuits (ICs) - Logic - Flip Flops Temperature Range - Operating: -40°C ~ 125°C (TA) Fake Threat In the Open Market: 56 pct. Type: D-Type MSL Level: 1 (Unlimited) Mfr: Nexperia USA Inc. Series: 74AUP Package: Tape & Reel Product Status: Active Package / Case: 8-VFSOP (0.091", 2.30mm Width) Supplier Device Package: 8-VSSOP Base Product Number: 74AUP2G80 Mounting Type: Surface Mount HTSUS: 8542.39.0001 REACH Status: REACH Unaffected ECCN: EAR99 Function: Standard Voltage - Supply: 0.8V ~ 3.6V Output Type: Inverted Clock Frequency: 309 MHz Current - Quiescent (Iq): 500 nA Current - Output High, Low: 4mA, 4mA Max Propagation Delay @ V, Max CL: 6.4ns @ 3.3V, 30pF Number of Elements: 2 Number of Bits per Element: 1 Trigger Type: Positive Edge Input Capacitance: 0.6 pF

Win Source Part Number: 1370980-74AUP2G80DC,125
Category: Integrated Circuits (ICs) - Logic - Flip Flops
Temperature Range - Operating: -40°C ~ 125°C (TA)
Fake Threat In the Open Market: 56 pct.
Type: D-Type
MSL Level: 1 (Unlimited)
Mfr: Nexperia USA Inc.
Series: 74AUP
Package: Tape & Reel
Product Status: Active
Package / Case: 8-VFSOP (0.091", 2.30mm Width)
Supplier Device Package: 8-VSSOP
Base Product Number: 74AUP2G80
Mounting Type: Surface Mount
HTSUS: 8542.39.0001
REACH Status: REACH Unaffected
ECCN: EAR99
Function: Standard
Voltage - Supply: 0.8V ~ 3.6V
Output Type: Inverted
Clock Frequency: 309 MHz
Current - Quiescent (Iq): 500 nA
Current - Output High, Low: 4mA, 4mA
Max Propagation Delay @ V, Max CL: 6.4ns @ 3.3V, 30pF
Number of Elements: 2
Number of Bits per Element: 1
Trigger Type: Positive Edge
Input Capacitance: 0.6 pF

Buy Now Datasheet
Flip-Flop, D-Type, 309Mhz, Vssop-8; Logic Family / Base Number Nexperia - 85X2782 - Newark, An Avnet Company
Chicago, IL, United States
Flip-Flop, D-Type, 309Mhz, Vssop-8; Logic Family / Base Number Nexperia
85X2782
Flip-Flop, D-Type, 309Mhz, Vssop-8; Logic Family / Base Number Nexperia 85X2782
FLIP-FLOP, D-TYPE, 309MHZ, VSSOP-8; Logic Family / Base Number:74AUP2G80; Flip-Flop Type:D; Propagation Delay:-; Frequency:309MHz; Output Current:20mA; Logic Case Style:VSSOP; No. of Pins:8Pins; Trigger Type:Positive Edge; IC Output RoHS Compliant: Yes

FLIP-FLOP, D-TYPE, 309MHZ, VSSOP-8; Logic Family / Base Number:74AUP2G80; Flip-Flop Type:D; Propagation Delay:-; Frequency:309MHz; Output Current:20mA; Logic Case Style:VSSOP; No. of Pins:8Pins; Trigger Type:Positive Edge; IC Output RoHS Compliant: Yes

Supplier's Site Datasheet
Flip Flops - 74AUP2G80DC,125 - Quarktwin Technology Ltd.
Shenzhen, Guangdong, China
Flip Flop 2 Element D-Type 1 Bit Positive Edge 8-VFSOP (0.091", 2.30mm Width)

Flip Flop 2 Element D-Type 1 Bit Positive Edge 8-VFSOP (0.091", 2.30mm Width)

Buy Now
Flip Flops - 74AUP2G80DC,125 - Quarktwin Technology Ltd.
Shenzhen, Guangdong, China
Flip Flop 2 Element D-Type 1 Bit Positive Edge 8-VFSOP (0.091", 2.30mm Width)

Flip Flop 2 Element D-Type 1 Bit Positive Edge 8-VFSOP (0.091", 2.30mm Width)

Buy Now Datasheet
Integrated Circuits (ICs) - Logic - Flip Flops - 74AUP2G80DC,125 - Shenzhen Shengyu Electronics Technology Limited
Futian, China
Integrated Circuits (ICs) - Logic - Flip Flops
74AUP2G80DC,125
Integrated Circuits (ICs) - Logic - Flip Flops 74AUP2G80DC,125
IC FF D-TYPE DUAL 1BIT 8VSSOP

IC FF D-TYPE DUAL 1BIT 8VSSOP

Supplier's Site
Logic - Flip Flops - 74AUP2G80DC,125 - Lingto Electronic Limited
Shenzhen, China
Logic - Flip Flops
74AUP2G80DC,125
Logic - Flip Flops 74AUP2G80DC,125
IC FF D-TYPE DUAL 1BIT 8VSSOP

IC FF D-TYPE DUAL 1BIT 8VSSOP

Supplier's Site Datasheet

Technical Specifications

  Nexperia B.V. DigiKey Win Source Electronics Newark, An Avnet Company Quarktwin Technology Ltd. Shenzhen Shengyu Electronics Technology Limited Lingto Electronic Limited
Product Category Flip-Flops Flip-Flops Flip-Flops Flip-Flops Flip-Flops Flip-Flops Flip-Flops
Product Number 74AUP2G80DC,125 1727-7901-1-ND 1370980-74AUP2G80DC,125 85X2782 74AUP2G80DC,125 74AUP2G80DC,125 74AUP2G80DC,125
Product Name Low-power dual D-type flip-flop; positive-edge trigger Flip Flops Integrated Circuits (ICs) - Logic - Flip Flops Flip-Flop, D-Type, 309Mhz, Vssop-8; Logic Family / Base Number Nexperia Flip Flops Integrated Circuits (ICs) - Logic - Flip Flops Logic - Flip Flops
Flip-Flop Type D D D
Triggering Positive-edge Triggered Positive-edge Triggered Positive-edge Triggered; Positive Edge
Supply Voltage +4.6 0.8V ~ 3.6V 0.8V ~ 3.6V 3.6V; 0.8V ~ 3.6V
Features ESD Protection
Operating Temperature 125 C (257 F) -40 to 125 C (-40 to 257 F) -40 to 125 C (-40 to 257 F) -40 to 125 C (-40 to 257 F)
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