Nexperia B.V. Low-power dual D-type flip-flop; positive-edge trigger 74AUP2G79DC-Q100H

Description
The 74AUP2G79-Q100 provides the dual positive-edge triggered D-type flip-flop. Information on the data input (nD) is transferred to the nQ output on the LOW-to-HIGH transition of the clock pulse (nCP). The nD input must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing a damaging backflow current through the device when it is powered down. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from -40 °C to +85 °C and from -40 °C to +125 °C Wide supply voltage range from 0.8 V to 3.6 V High noise immunity Complies with JEDEC standards: JESD8-12 (0.8 V to 1.3 V) JESD8-11 (0.9 V to 1.65 V) JESD8-7 (1.2 V to 1.95 V) JESD8-5 (1.8 V to 2.7 V) JESD8-B (2.7 V to 3.6 V) Low static power consumption; ICC = 0.9 μA (maximum) Latch-up performance exceeds 100 mA per JESD78 Class II Inputs accept voltages up to 3.6 V Low noise overshoot and undershoot < 10 % of VCC IOFF circuitry provides partial Power-down mode operation ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
  • Low-power dual D-type flip-flop; positive-edge trigger - 74AUP2G79DC-Q100H - Nexperia B.V.
    Nexperia B.V.
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  • Flip Flops - 74AUP2G79DC-Q100H - Quarktwin Technology Ltd.
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  • Logic - Flip Flops - 74AUP2G79DC-Q100H - Lingto Electronic Limited
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  • Integrated Circuits (ICs) - Logic - Flip Flops - 74AUP2G79DC-Q100H - Shenzhen Shengyu Electronics Technology Limited
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Request a Quote Datasheet
Description
The 74AUP2G79-Q100 provides the dual positive-edge triggered D-type flip-flop. Information on the data input (nD) is transferred to the nQ output on the LOW-to-HIGH transition of the clock pulse (nCP). The nD input must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing a damaging backflow current through the device when it is powered down. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from -40 °C to +85 °C and from -40 °C to +125 °C Wide supply voltage range from 0.8 V to 3.6 V High noise immunity Complies with JEDEC standards: JESD8-12 (0.8 V to 1.3 V) JESD8-11 (0.9 V to 1.65 V) JESD8-7 (1.2 V to 1.95 V) JESD8-5 (1.8 V to 2.7 V) JESD8-B (2.7 V to 3.6 V) Low static power consumption; ICC = 0.9 μA (maximum) Latch-up performance exceeds 100 mA per JESD78 Class II Inputs accept voltages up to 3.6 V Low noise overshoot and undershoot < 10 % of VCC IOFF circuitry provides partial Power-down mode operation ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
Request a Quote Datasheet

Suppliers

Company
Product
Description
Supplier Links
Low-power dual D-type flip-flop; positive-edge trigger - 74AUP2G79DC-Q100H - Nexperia B.V.
Nexperia B.V.
Nijmegen, Netherlands
Low-power dual D-type flip-flop; positive-edge trigger
74AUP2G79DC-Q100H
Low-power dual D-type flip-flop; positive-edge trigger 74AUP2G79DC-Q100H
The 74AUP2G79-Q100 provides the dual positive-edge triggered D-type flip-flop. Information on the data input (nD) is transferred to the nQ output on the LOW-to-HIGH transition of the clock pulse (nCP). The nD input must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing a damaging backflow current through the device when it is powered down. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from -40 °C to +85 °C and from -40 °C to +125 °C Wide supply voltage range from 0.8 V to 3.6 V High noise immunity Complies with JEDEC standards: JESD8-12 (0.8 V to 1.3 V) JESD8-11 (0.9 V to 1.65 V) JESD8-7 (1.2 V to 1.95 V) JESD8-5 (1.8 V to 2.7 V) JESD8-B (2.7 V to 3.6 V) Low static power consumption; ICC = 0.9 μA (maximum) Latch-up performance exceeds 100 mA per JESD78 Class II Inputs accept voltages up to 3.6 V Low noise overshoot and undershoot < 10 % of VCC IOFF circuitry provides partial Power-down mode operation ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

The 74AUP2G79-Q100 provides the dual positive-edge triggered D-type flip-flop. Information on the data input (nD) is transferred to the nQ output on the LOW-to-HIGH transition of the clock pulse (nCP). The nD input must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation.

Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.

This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.

This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing a damaging backflow current through the device when it is powered down.

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.

Features and benefits

  • Automotive product qualification in accordance with AEC-Q100 (Grade 1)
    • Specified from -40 °C to +85 °C and from -40 °C to +125 °C
  • Wide supply voltage range from 0.8 V to 3.6 V
  • High noise immunity
  • Complies with JEDEC standards:
    • JESD8-12 (0.8 V to 1.3 V)
    • JESD8-11 (0.9 V to 1.65 V)
    • JESD8-7 (1.2 V to 1.95 V)
    • JESD8-5 (1.8 V to 2.7 V)
    • JESD8-B (2.7 V to 3.6 V)
  • Low static power consumption; ICC = 0.9 μA (maximum)
  • Latch-up performance exceeds 100 mA per JESD78 Class II
  • Inputs accept voltages up to 3.6 V
  • Low noise overshoot and undershoot < 10 % of VCC
  • IOFF circuitry provides partial Power-down mode operation
  • ESD protection:
    • HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V
    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
Supplier's Site Datasheet
Flip Flops - 1727-74AUP2G79DC-Q100HDKR-ND - DigiKey
DigiKey
Thief River Falls, MN, United States
Flip Flops
1727-74AUP2G79DC-Q100HDKR-ND
Flip Flops 1727-74AUP2G79DC-Q100HDKR-ND
"Flip Flop 2 Element D-Type 1 Bit Positive Edge 8-VFSOP (0.091"", 2.30mm Width)"

"Flip Flop 2 Element D-Type 1 Bit Positive Edge 8-VFSOP (0.091"", 2.30mm Width)"

Buy Now Datasheet
Flip Flops - 1727-74AUP2G79DC-Q100HCT-ND - DigiKey
DigiKey
Thief River Falls, MN, United States
Flip Flops
1727-74AUP2G79DC-Q100HCT-ND
Flip Flops 1727-74AUP2G79DC-Q100HCT-ND
"Flip Flop 2 Element D-Type 1 Bit Positive Edge 8-VFSOP (0.091"", 2.30mm Width)"

"Flip Flop 2 Element D-Type 1 Bit Positive Edge 8-VFSOP (0.091"", 2.30mm Width)"

Buy Now Datasheet
Flip Flops - 1727-74AUP2G79DC-Q100HTR-ND - DigiKey
DigiKey
Thief River Falls, MN, United States
Flip Flops
1727-74AUP2G79DC-Q100HTR-ND
Flip Flops 1727-74AUP2G79DC-Q100HTR-ND
"Flip Flop 2 Element D-Type 1 Bit Positive Edge 8-VFSOP (0.091"", 2.30mm Width)"

"Flip Flop 2 Element D-Type 1 Bit Positive Edge 8-VFSOP (0.091"", 2.30mm Width)"

Buy Now Datasheet
Flip Flops - 74AUP2G79DC-Q100H - Quarktwin Technology Ltd.
Quarktwin Technology Ltd.
Shenzhen, Guangdong, China
Flip Flops
74AUP2G79DC-Q100H
Flip Flops 74AUP2G79DC-Q100H
Flip Flop 2 Element D-Type 1 Bit Positive Edge 8-VFSOP (0.091", 2.30mm Width)

Flip Flop 2 Element D-Type 1 Bit Positive Edge 8-VFSOP (0.091", 2.30mm Width)

Buy Now Datasheet
Logic - Flip Flops - 74AUP2G79DC-Q100H - Lingto Electronic Limited
Lingto Electronic Limited
Shenzhen, China
Logic - Flip Flops
74AUP2G79DC-Q100H
Logic - Flip Flops 74AUP2G79DC-Q100H
IC FF D-TYPE DUAL 1BIT 8VSSOP

IC FF D-TYPE DUAL 1BIT 8VSSOP

Supplier's Site Datasheet
Integrated Circuits (ICs) - Logic - Flip Flops - 74AUP2G79DC-Q100H - Shenzhen Shengyu Electronics Technology Limited
Shenzhen Shengyu Electronics Technology Limited
Futian, China
Integrated Circuits (ICs) - Logic - Flip Flops
74AUP2G79DC-Q100H
Integrated Circuits (ICs) - Logic - Flip Flops 74AUP2G79DC-Q100H
IC FF D-TYPE DUAL 1BIT 8VSSOP

IC FF D-TYPE DUAL 1BIT 8VSSOP

Supplier's Site

Technical Specifications

  Nexperia B.V. DigiKey Quarktwin Technology Ltd. Lingto Electronic Limited Shenzhen Shengyu Electronics Technology Limited
Product Category Flip-Flops Flip-Flops Flip-Flops Flip-Flops Flip-Flops
Product Number 74AUP2G79DC-Q100H 1727-74AUP2G79DC-Q100HDKR-ND 74AUP2G79DC-Q100H 74AUP2G79DC-Q100H 74AUP2G79DC-Q100H
Product Name Low-power dual D-type flip-flop; positive-edge trigger Flip Flops Flip Flops Logic - Flip Flops Integrated Circuits (ICs) - Logic - Flip Flops
Flip-Flop Type D D D
Triggering Positive-edge Triggered Positive-edge Triggered
Supply Voltage +4.6 0.8V ~ 3.6V 3.6V; 0.8V ~ 3.6V
Features ESD Protection
Operating Temperature 125 C (257 F) -40 to 125 C (-40 to 257 F) -40 to 125 C (-40 to 257 F)
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