The 74ALVCH16823DGG,11 is an 18-bit D-type flip-flop designed for bus-oriented applications, featuring separate D-type inputs and 3-state outputs. It operates within a supply voltage range of 1.2V to 3.6V and is compliant with JEDEC standard no. 8-1A. The device supports low power consumption typical of CMOS technology and can directly interface with TTL levels. It offers a current drive capability of ¬±24 mA at 3.0V and has a maximum clock frequency of 300 MHz at 2.5V and 350 MHz at 3.3V. The flip-flop includes active bus hold circuitry to maintain valid logic levels on unused inputs, eliminating the need for external pull-up resistors. Each section of the device has a clock input, output-enable input, master reset input, and clock-enable input, allowing for flexible operation. The 74ALVCH16823DGG,11 is available in a 56-pin TSSOP package and operates within a temperature range of -40¬8C to +85¬8C, making it suitable for various applications in automotive, industrial, and consumer electronics.
The 74ALVCH16823 is an 18-bit edge-triggered flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. Incorporates bushold data inputs which eliminate the need for external pull-up resistors to hold unused inputs. The 74ALVCH16823 consists of two sections of nine edge-triggered flip-flops. A clock (nCP) input, an output-enable (nOE) input, a master reset (nMR) input and a clock-enable (nCE) input are provided for each total 9-bit section.
With the clock-enable (nCE) input LOW, the D-type flip-flops will store the state of their individual nDn-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH nCP transition. Taking nCEHIGH disables the clock buffer, thus latching the outputs. Taking the master reset (nMR) input LOW causes all the nQn outputs to go LOW independently of the clock.
When nOEis LOW, the contents of the flip-flops are available at the outputs. When the nOEis HIGH, the outputs go to the high impedance OFF-state. Operation of the nOEinput does not affect the state of flip-flops.
Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
Features and benefits
"Flip Flop 2 Element D-Type 9 Bit Positive Edge 56-TFSOP (0.240"", 6.10mm Width)"
Flip Flop 2 Element D-Type 9 Bit Positive Edge 56-TFSOP (0.240", 6.10mm Width)
IC FF D-TYPE DUAL 9BIT 56TSSOP
IC FF D-TYPE DUAL 9BIT 56TSSOP
| Nexperia B.V. | DigiKey | Quarktwin Technology Ltd. | Shenzhen Shengyu Electronics Technology Limited | Lingto Electronic Limited | |
|---|---|---|---|---|---|
| Product Category | Flip-Flops | Flip-Flops | Flip-Flops | Flip-Flops | Flip-Flops |
| Product Number | 74ALVCH16823DGG,11 | 1727-74ALVCH16823DGG,11TR-ND | 74ALVCH16823DGG,11 | 74ALVCH16823DGG,11 | 74ALVCH16823DGG,11 |
| Product Name | 18-bit bus-interface D-type flip-flop with reset and enable; 3-state | Flip Flops | Flip Flops | Integrated Circuits (ICs) - Logic - Flip Flops | Logic - Flip Flops |
| Flip-Flop Type | D | D | D | ||
| Supply Voltage | +4.6 | 2.3V ~ 2.7V, 3V ~ 3.6V | 3V; 3.6V; 2.3V ~ 2.7V, 3V ~ 3.6V | ||
| Output Characteristics | 3-State; OE | 3-State | |||
| Features | ESD Protection | ||||
| Operating Temperature | 85 C (185 F) | -40 to 85 C (-40 to 185 F) | -40 to 85 C (-40 to 185 F) |
