Nexperia B.V. Dual JK flip-flop with set and reset; positive-edge-trigger 74HCT109PW,118

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Dual JK flip-flop with set and reset; positive-edge-trigger - 74HCT109PW,118 - Nexperia B.V.
Nijmegen, Netherlands
Dual JK flip-flop with set and reset; positive-edge-trigger
74HCT109PW,118
Dual JK flip-flop with set and reset; positive-edge-trigger 74HCT109PW,118
The 74HC109; 74HCT109 is a dual positive edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) inputs, set (SD) and reset (RD) inputs and complementary Q and Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. The J and K inputs control the state changes of the flip-flops as described in the mode select function table. The J and K inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. The JK design allows operation as a D-type flip-flop by connecting the J and K inputs together. This device features reduced input threshold levels to allow interfacing to TTL logic levels. Inputs also include clamp diodes, this enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. Features and benefits J and K inputs for easy D-type flip-flop Toggle flip-flop or "do nothing" mode Wide supply voltage range: For 74HC109: from 2.0 V to 6.0 V For 74HCT109: from 4.5 V to 5.5 V CMOS low power dissipation High noise immunity Input levels: For 74HC109: CMOS level For 74HCT109: TTL level Latch-up performance exceeds 100 mA per JESD 78 Class II Level B 74HC109 complies with JEDEC standards: JESD8C (2.7 V to 3.6 V) JESD7A (2.0 V to 6.0 V) 74HCT109 complies with JEDEC standard JESD7A (2.0 V to 6.0 V) ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Specified from -40 °C to +85 °C and from -40 °C to +125 °C

The 74HC109; 74HCT109 is a dual positive edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) inputs, set (SD) and reset (RD) inputs and complementary Q and Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. The J and K inputs control the state changes of the flip-flops as described in the mode select function table. The J and K inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. The JK design allows operation as a D-type flip-flop by connecting the J and K inputs together. This device features reduced input threshold levels to allow interfacing to TTL logic levels. Inputs also include clamp diodes, this enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.

Features and benefits

  • J and K inputs for easy D-type flip-flop
  • Toggle flip-flop or "do nothing" mode
  • Wide supply voltage range:
    • For 74HC109: from 2.0 V to 6.0 V
    • For 74HCT109: from 4.5 V to 5.5 V
  • CMOS low power dissipation
  • High noise immunity
  • Input levels:
    • For 74HC109: CMOS level
    • For 74HCT109: TTL level
  • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
  • 74HC109 complies with JEDEC standards:
    • JESD8C (2.7 V to 3.6 V)
    • JESD7A (2.0 V to 6.0 V)
  • 74HCT109 complies with JEDEC standard JESD7A (2.0 V to 6.0 V)
  • ESD protection:
    • HBM JESD22-A114F exceeds 2000 V
    • MM JESD22-A115-A exceeds 200 V
  • Specified from -40 °C to +85 °C and from -40 °C to +125 °C
Supplier's Site Datasheet
Flip Flops - 1727-74HCT109PW,118TR-ND - DigiKey
Thief River Falls, MN, United States
Flip Flop 2 Element JK Type 1 Bit Positive Edge 16-TSSOP (0.173", 4.40mm Width)

Flip Flop 2 Element JK Type 1 Bit Positive Edge 16-TSSOP (0.173", 4.40mm Width)

Supplier's Site Datasheet
Flip Flops - 1727-74HCT109PW,118DKR-ND - DigiKey
Thief River Falls, MN, United States
IC FF JK TYPE DUAL 1BIT 16TSSOP

IC FF JK TYPE DUAL 1BIT 16TSSOP

Supplier's Site Datasheet
Flip Flops - 1727-74HCT109PW,118CT-ND - DigiKey
Thief River Falls, MN, United States
IC FF JK TYPE DUAL 1BIT 16TSSOP

IC FF JK TYPE DUAL 1BIT 16TSSOP

Supplier's Site Datasheet
Yishun, Singapore
Logic - Logic - Flip Flops - 74HCT109PW,118
765473-74HCT109PW,118
Logic - Logic - Flip Flops - 74HCT109PW,118 765473-74HCT109PW,118
Manufacturer: Nexperia USA Inc. Win Source Part Number: 765473-74HCT109PW,11 8 Series: 74HCT Packaging: Reel package Type: JK Type Operating Temperature Range: -40°C ~ 125°C (TA) Package: 16-TSSOP (0.173", 4.40mm Width) Mounting: SMD Output Type: Differential Current - Output High, Low: 4mA, 4mA Operating Supply Voltage: 4.5 V ~ 5.5 V Function: Set(Preset) and Reset Number of Elements: 2 Number of Bits per Element: 1 Max Propagation Delay @ V, Max CL: 35ns @ 6V, 50pF Current - Quiescent: 4μA Input Capacitance: 3.5pF Family Name: 74HCT109 Categories: Integrated Circuits (ICs) Clock Frequency: 55MHz Alternative Parts (Cross-Reference): CD74HCT109PW; CD74HCT109PWR; 74HCT109N,652; Introduction Date: December 01, 1990 ECCN: EAR99 Country of Origin: Thailand Estimated EOL Date: 2026 Halogen Free: Compliant Popularity: Medium Fake Threat In the Open Market: 39 pct. Supply and Demand Status: Balance

Manufacturer: Nexperia USA Inc.
Win Source Part Number: 765473-74HCT109PW,118
Series: 74HCT
Packaging: Reel package
Type: JK Type
Operating Temperature Range: -40°C ~ 125°C (TA)
Package: 16-TSSOP (0.173", 4.40mm Width)
Mounting: SMD
Output Type: Differential
Current - Output High, Low: 4mA, 4mA
Operating Supply Voltage: 4.5 V ~ 5.5 V
Function: Set(Preset) and Reset
Number of Elements: 2
Number of Bits per Element: 1
Max Propagation Delay @ V, Max CL: 35ns @ 6V, 50pF
Current - Quiescent: 4μA
Input Capacitance: 3.5pF
Family Name: 74HCT109
Categories: Integrated Circuits (ICs)
Clock Frequency: 55MHz
Alternative Parts (Cross-Reference): CD74HCT109PW; CD74HCT109PWR; 74HCT109N,652;
Introduction Date: December 01, 1990
ECCN: EAR99
Country of Origin: Thailand
Estimated EOL Date: 2026
Halogen Free: Compliant
Popularity: Medium
Fake Threat In the Open Market: 39 pct.
Supply and Demand Status: Balance

Supplier's Site Datasheet
Logic - Flip Flops - 74HCT109PW,118 - Lingto Electronic Limited
Shenzhen, China
Logic - Flip Flops
74HCT109PW,118
Logic - Flip Flops 74HCT109PW,118
IC FF JK TYPE DUAL 1BIT 16TSSOP

IC FF JK TYPE DUAL 1BIT 16TSSOP

Supplier's Site Datasheet
Integrated Circuits (ICs) - Logic - Flip Flops - 74HCT109PW,118 - Shenzhen Shengyu Electronics Technology Limited
Futian, China
Integrated Circuits (ICs) - Logic - Flip Flops
74HCT109PW,118
Integrated Circuits (ICs) - Logic - Flip Flops 74HCT109PW,118
IC FF JK TYPE DUAL 1BIT 16TSSOP

IC FF JK TYPE DUAL 1BIT 16TSSOP

Supplier's Site
Flip Flops - 74HCT109PW,118 - Quarktwin Technology Ltd.
Shenzhen, Guangdong, China
Flip Flops
74HCT109PW,118
Flip Flops 74HCT109PW,118
Flip Flop 2 Element JK Type 1 Bit Positive Edge 16-TSSOP (0.173", 4.40mm Width)

Flip Flop 2 Element JK Type 1 Bit Positive Edge 16-TSSOP (0.173", 4.40mm Width)

Supplier's Site Datasheet
 - 74HCT109PW,118 - Rochester Electronics
Newburyport, MA, United States
Nexperia 74HCT109PW - J-Kbar Flip-Flop, HCT Series, 2-Func, Positive Edge Triggered, 2-Bit, Complementary Output, TSSOP-16

Nexperia 74HCT109PW - J-Kbar Flip-Flop, HCT Series, 2-Func, Positive Edge Triggered, 2-Bit, Complementary Output, TSSOP-16

Supplier's Site Datasheet

Technical Specifications

  Nexperia B.V. DigiKey Win Source Electronics Lingto Electronic Limited Shenzhen Shengyu Electronics Technology Limited Quarktwin Technology Ltd. Rochester Electronics
Product Category Flip-Flops Flip-Flops Flip-Flops Flip-Flops Flip-Flops Flip-Flops Flip-Flops
Product Number 74HCT109PW,118 1727-74HCT109PW,118TR-ND 765473-74HCT109PW,118 74HCT109PW,118 74HCT109PW,118 74HCT109PW,118 74HCT109PW,118
Product Name Dual JK flip-flop with set and reset; positive-edge-trigger Flip Flops Logic - Logic - Flip Flops - 74HCT109PW,118 Logic - Flip Flops Integrated Circuits (ICs) - Logic - Flip Flops Flip Flops
Flip-Flop Type J-K J-K J-K
Triggering Positive-edge Triggered Positive-edge Triggered Positive-edge Triggered
Supply Voltage 5V; 4.5 - 5.5 4.5V ~ 5.5V 4.5 V ~ 5.5 V 4.5V ~ 5.5V
Features ESD Protection
Propagation Delay 17 ns 35 ns 35 ns
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