Nexperia B.V. Dual D-type flip-flop with set and reset; positive-edge trigger 74AHCT74D,118

The 74AHC74; 74AHCT74 is a high-speed Si-gate CMOS device and is pin compatible with Low-Power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A.

The 74AHC74; 74AHCT74 is a dual positive-edge triggered, D-type flip-flop with individual data inputs (D), clock inputs (CP), set inputs (SD) and reset inputs (RD). It also has complementary outputs (Q and Q).

The set and reset are asynchronous active LOW inputs that operate independent of the clock input. Information on the data input is transferred to the Q output on the LOW to HIGH transition of the clock pulse. The data inputs must be stable one set-up time prior to the LOW to HIGH clock transition for predictable operation.

Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.

Features and benefits

• Balanced propagation delays
• All inputs have Schmitt-trigger actions
• Inputs accept voltages higher than V_CC
• Input levels:
• For 74AHC74: CMOS level
• For 74AHCT74: TTL level
• ESD protection:
• HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
• CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
• Multiple package options
• Specified from -40 °C to +85 °C and from -40 °C to +125 °C

Win Source Part Number: 1370951-74AHCT74D,118
Category: Integrated Circuits (ICs) - Logic - Flip Flops
Temperature Range - Operating: -40°C ~ 125°C (TA)
Fake Threat In the Open Market: 34 pct.
Type: D-Type
MSL Level: 1 (Unlimited)
Mfr: Nexperia USA Inc.
Series: 74AHCT
Package: Tape & Reel
Product Status: Active
Package / Case: 14-SOIC (0.154", 3.90mm Width)
Supplier Device Package: 14-SO
Base Product Number: 74AHCT74
Mounting Type: Surface Mount
HTSUS: 8542.39.0001
REACH Status: REACH Unaffected
ECCN: EAR99
Function: Set(Preset) and Reset
Voltage - Supply: 4.5V ~ 5.5V
Output Type: Complementary
Clock Frequency: 140 MHz
Current - Quiescent (Iq): 2 µA
Current - Output High, Low: 8mA, 8mA
Max Propagation Delay @ V, Max CL: 8.8ns @ 5V, 50pF
Number of Elements: 2
Number of Bits per Element: 1
Trigger Type: Positive Edge
Input Capacitance: 3 pF

"Flip Flop 2 Element D-Type 1 Bit Positive Edge 14-SOIC (0.154"", 3.90mm Width)"

"Flip Flop 2 Element D-Type 1 Bit Positive Edge 14-SOIC (0.154"", 3.90mm Width)"

"Flip Flop 2 Element D-Type 1 Bit Positive Edge 14-SOIC (0.154"", 3.90mm Width)"