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Nexperia B.V. Dual D-type flip-flop with set and reset; positive-edge trigger 74AHCT74BQ,115

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Description
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Dual D-type flip-flop with set and reset; positive-edge trigger - 74AHCT74BQ,115 - Nexperia B.V.
Nijmegen, Netherlands
Dual D-type flip-flop with set and reset; positive-edge trigger
74AHCT74BQ,115
Dual D-type flip-flop with set and reset; positive-edge trigger 74AHCT74BQ,115
The 74AHC74; 74AHCT74 is a high-speed Si-gate CMOS device and is pin compatible with Low-Power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. The 74AHC74; 74AHCT74 is a dual positive-edge triggered, D-type flip-flop with individual data inputs (D), clock inputs (CP), set inputs (SD) and reset inputs (RD). It also has complementary outputs (Q and Q). The set and reset are asynchronous active LOW inputs that operate independent of the clock input. Information on the data input is transferred to the Q output on the LOW to HIGH transition of the clock pulse. The data inputs must be stable one set-up time prior to the LOW to HIGH clock transition for predictable operation. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. Features and benefits Balanced propagation delays All inputs have Schmitt-trigger actions Inputs accept voltages higher than VCC Input levels: For 74AHC74: CMOS level For 74AHCT74: TTL level ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V Multiple package options Specified from -40 °C to +85 °C and from -40 °C to +125 °C

The 74AHC74; 74AHCT74 is a high-speed Si-gate CMOS device and is pin compatible with Low-Power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A.

The 74AHC74; 74AHCT74 is a dual positive-edge triggered, D-type flip-flop with individual data inputs (D), clock inputs (CP), set inputs (SD) and reset inputs (RD). It also has complementary outputs (Q and Q).

The set and reset are asynchronous active LOW inputs that operate independent of the clock input. Information on the data input is transferred to the Q output on the LOW to HIGH transition of the clock pulse. The data inputs must be stable one set-up time prior to the LOW to HIGH clock transition for predictable operation.

Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.

Features and benefits

  • Balanced propagation delays
  • All inputs have Schmitt-trigger actions
  • Inputs accept voltages higher than VCC
  • Input levels:
    • For 74AHC74: CMOS level
    • For 74AHCT74: TTL level
  • ESD protection:
    • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
  • Multiple package options
  • Specified from -40 °C to +85 °C and from -40 °C to +125 °C
Supplier's Site Datasheet
Integrated Circuits (ICs) - Logic - Flip Flops - 74AHCT74BQ,115 - Shenzhen Shengyu Electronics Technology Limited
Futian, China
Integrated Circuits (ICs) - Logic - Flip Flops
74AHCT74BQ,115
Integrated Circuits (ICs) - Logic - Flip Flops 74AHCT74BQ,115
IC FF D-TYPE DUAL 1BIT 14DHVQFN

IC FF D-TYPE DUAL 1BIT 14DHVQFN

Supplier's Site
Logic - Flip Flops - 74AHCT74BQ,115 - Lingto Electronic Limited
Shenzhen, China
Logic - Flip Flops
74AHCT74BQ,115
Logic - Flip Flops 74AHCT74BQ,115
IC FF D-TYPE DUAL 1BIT 14DHVQFN

IC FF D-TYPE DUAL 1BIT 14DHVQFN

Supplier's Site Datasheet
 - 74AHCT74BQ,115 - Rochester Electronics
Newburyport, MA, United States
74AHCT74 - Dual D-type flip-flop with set and reset; positive-edge trigger

74AHCT74 - Dual D-type flip-flop with set and reset; positive-edge trigger

Supplier's Site Datasheet
Flip Flops - 1727-74AHCT74BQ,115CT-ND - DigiKey
Thief River Falls, MN, United States
IC FF D-TYPE DUAL 1BIT 14DHVQFN

IC FF D-TYPE DUAL 1BIT 14DHVQFN

Supplier's Site Datasheet
Flip Flops - 1727-74AHCT74BQ,115DKR-ND - DigiKey
Thief River Falls, MN, United States
IC FF D-TYPE DUAL 1BIT 14DHVQFN

IC FF D-TYPE DUAL 1BIT 14DHVQFN

Supplier's Site Datasheet
Flip Flops - 1727-74AHCT74BQ,115TR-ND - DigiKey
Thief River Falls, MN, United States
Flip Flop 2 Element D-Type 1 Bit Positive Edge 14-VFQFN Exposed Pad

Flip Flop 2 Element D-Type 1 Bit Positive Edge 14-VFQFN Exposed Pad

Supplier's Site Datasheet
Flip Flops - 74AHCT74BQ,115 - Quarktwin Technology Ltd.
Shenzhen, Guangdong, China
Flip Flops
74AHCT74BQ,115
Flip Flops 74AHCT74BQ,115
Flip Flop 2 Element D-Type 1 Bit Positive Edge 14-VFQFN Exposed Pad

Flip Flop 2 Element D-Type 1 Bit Positive Edge 14-VFQFN Exposed Pad

Supplier's Site Datasheet

Technical Specifications

  Nexperia B.V. Shenzhen Shengyu Electronics Technology Limited Lingto Electronic Limited Rochester Electronics DigiKey Quarktwin Technology Ltd.
Product Category Flip-Flops Flip-Flops Flip-Flops Flip-Flops Flip-Flops Flip-Flops
Product Number 74AHCT74BQ,115 74AHCT74BQ,115 74AHCT74BQ,115 74AHCT74BQ,115 1727-74AHCT74BQ,115CT-ND 74AHCT74BQ,115
Product Name Dual D-type flip-flop with set and reset; positive-edge trigger Integrated Circuits (ICs) - Logic - Flip Flops Logic - Flip Flops Flip Flops Flip Flops
Flip-Flop Type D D D
Triggering Positive-edge Triggered Positive-edge Triggered Positive-edge Triggered
Supply Voltage 5V; 4.5 - 5.5 4.5V ~ 5.5V 4.5V ~ 5.5V
Features ESD Protection
Propagation Delay 3.3 ns 8.8 ns
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