Nexperia B.V. Octal D-type flip-flop with reset; positive-edge trigger 74AHC273PW,118

Description
The 74AHC273; 74AHCT273 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding D inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A LOW on MRforces the outputs LOW independently of clock and data inputs. Inputs are overvoltage tolerant. This feature allows the use of these devices as translators in mixed voltage environments. Features and benefits Wide supply voltage range from 2.0 to 5.5 V Overvoltage tolerant inputs to 5.5 V High noise immunity CMOS low power dissipation Balanced propagation delays All inputs have Schmitt-trigger actions Ideal buffer for MOS microcontroller or memory Common clock and master reset Latch-up performance exceeds 100 mA per JESD 78 Class II Level A Input levels: For 74AHC273: CMOS level For 74AHCT273: TTL level ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V Multiple package options Specified from -40 °C to +85 °C and from -40 °C to +125 °C
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Description
The 74AHC273; 74AHCT273 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding D inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A LOW on MRforces the outputs LOW independently of clock and data inputs. Inputs are overvoltage tolerant. This feature allows the use of these devices as translators in mixed voltage environments. Features and benefits Wide supply voltage range from 2.0 to 5.5 V Overvoltage tolerant inputs to 5.5 V High noise immunity CMOS low power dissipation Balanced propagation delays All inputs have Schmitt-trigger actions Ideal buffer for MOS microcontroller or memory Common clock and master reset Latch-up performance exceeds 100 mA per JESD 78 Class II Level A Input levels: For 74AHC273: CMOS level For 74AHCT273: TTL level ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V Multiple package options Specified from -40 °C to +85 °C and from -40 °C to +125 °C
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Suppliers

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Product
Description
Supplier Links
Octal D-type flip-flop with reset; positive-edge trigger - 74AHC273PW,118 - Nexperia B.V.
Nijmegen, Netherlands
Octal D-type flip-flop with reset; positive-edge trigger
74AHC273PW,118
Octal D-type flip-flop with reset; positive-edge trigger 74AHC273PW,118
The 74AHC273; 74AHCT273 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding D inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A LOW on MRforces the outputs LOW independently of clock and data inputs. Inputs are overvoltage tolerant. This feature allows the use of these devices as translators in mixed voltage environments. Features and benefits Wide supply voltage range from 2.0 to 5.5 V Overvoltage tolerant inputs to 5.5 V High noise immunity CMOS low power dissipation Balanced propagation delays All inputs have Schmitt-trigger actions Ideal buffer for MOS microcontroller or memory Common clock and master reset Latch-up performance exceeds 100 mA per JESD 78 Class II Level A Input levels: For 74AHC273: CMOS level For 74AHCT273: TTL level ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V Multiple package options Specified from -40 °C to +85 °C and from -40 °C to +125 °C

The 74AHC273; 74AHCT273 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding D inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A LOW on MRforces the outputs LOW independently of clock and data inputs. Inputs are overvoltage tolerant. This feature allows the use of these devices as translators in mixed voltage environments.

Features and benefits

  • Wide supply voltage range from 2.0 to 5.5 V
  • Overvoltage tolerant inputs to 5.5 V
  • High noise immunity
  • CMOS low power dissipation
  • Balanced propagation delays
  • All inputs have Schmitt-trigger actions
  • Ideal buffer for MOS microcontroller or memory
  • Common clock and master reset
  • Latch-up performance exceeds 100 mA per JESD 78 Class II Level A
  • Input levels:
    • For 74AHC273: CMOS level
    • For 74AHCT273: TTL level
  • ESD protection:
    • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
  • Multiple package options
  • Specified from -40 °C to +85 °C and from -40 °C to +125 °C
Supplier's Site Datasheet
 - 74AHC273PW,118 - Rochester Electronics
Newburyport, MA, United States
D Flip-Flop, AHC Series, 1-Func, Positive Edge Triggered, 8-Bit, True Output, CMOS, PDSO20

D Flip-Flop, AHC Series, 1-Func, Positive Edge Triggered, 8-Bit, True Output, CMOS, PDSO20

Supplier's Site Datasheet
Logic - Logic - Flip Flops - 74AHC273PW,118 - 1007487-74AHC273PW,118 - Win Source Electronics
Laguna Hills, CA, United States
Logic - Logic - Flip Flops - 74AHC273PW,118
1007487-74AHC273PW,118
Logic - Logic - Flip Flops - 74AHC273PW,118 1007487-74AHC273PW,118
Manufacturer: Nexperia USA Inc. Win Source Part Number: 1007487-74AHC273PW,1 18 Packaging: Reel - TR Type: D-Type Mounting: SMD (SMT) Output Type: Non-Inverted Current - Output High, Low: 8mA, 8mA Number of Elements: 1 Number of Bits per Element: 8 Max Propagation Delay @ V, Max CL: 11ns @ 5V, 50pF Trigger Type: Positive Edge Current - Quiescent: 4μA Input Capacitance: 3pF Categories: Integrated Circuits Status: Active Temperature Range - Operating: -40°C to 125°C (TA) Dimension: 20-TSSOP (0.173", 4.40mm Width) Purpose: Master Reset Supply Voltage - Operating: 2 V to 5.5 V Max Frequency: 110MHz Popularity: Medium Fake Threat In the Open Market: 60 pct. Supply and Demand Status: Sufficient

Manufacturer: Nexperia USA Inc.
Win Source Part Number: 1007487-74AHC273PW,118
Packaging: Reel - TR
Type: D-Type
Mounting: SMD (SMT)
Output Type: Non-Inverted
Current - Output High, Low: 8mA, 8mA
Number of Elements: 1
Number of Bits per Element: 8
Max Propagation Delay @ V, Max CL: 11ns @ 5V, 50pF
Trigger Type: Positive Edge
Current - Quiescent: 4μA
Input Capacitance: 3pF
Categories: Integrated Circuits
Status: Active
Temperature Range - Operating: -40°C to 125°C (TA)
Dimension: 20-TSSOP (0.173", 4.40mm Width)
Purpose: Master Reset
Supply Voltage - Operating: 2 V to 5.5 V
Max Frequency: 110MHz
Popularity: Medium
Fake Threat In the Open Market: 60 pct.
Supply and Demand Status: Sufficient

Buy Now Datasheet
Flip Flops - 1727-1966-2-ND - DigiKey
Thief River Falls, MN, United States
Flip Flops
1727-1966-2-ND
Flip Flops 1727-1966-2-ND
"Flip Flop 1 Element D-Type 8 Bit Positive Edge 20-TSSOP (0.173"", 4.40mm Width)"

"Flip Flop 1 Element D-Type 8 Bit Positive Edge 20-TSSOP (0.173"", 4.40mm Width)"

Buy Now Datasheet
Flip Flops - 1727-1966-6-ND - DigiKey
Thief River Falls, MN, United States
Flip Flops
1727-1966-6-ND
Flip Flops 1727-1966-6-ND
"Flip Flop 1 Element D-Type 8 Bit Positive Edge 20-TSSOP (0.173"", 4.40mm Width)"

"Flip Flop 1 Element D-Type 8 Bit Positive Edge 20-TSSOP (0.173"", 4.40mm Width)"

Buy Now Datasheet
Flip Flops - 1727-1966-1-ND - DigiKey
Thief River Falls, MN, United States
Flip Flops
1727-1966-1-ND
Flip Flops 1727-1966-1-ND
"Flip Flop 1 Element D-Type 8 Bit Positive Edge 20-TSSOP (0.173"", 4.40mm Width)"

"Flip Flop 1 Element D-Type 8 Bit Positive Edge 20-TSSOP (0.173"", 4.40mm Width)"

Buy Now Datasheet
Logic - Flip Flops - 74AHC273PW,118 - Lingto Electronic Limited
Shenzhen, China
Logic - Flip Flops
74AHC273PW,118
Logic - Flip Flops 74AHC273PW,118
IC FF D-TYPE SNGL 8BIT 20TSSOP

IC FF D-TYPE SNGL 8BIT 20TSSOP

Supplier's Site Datasheet
D Flip Flop, Octal, 4.2Ns, Tssop-20; Logic Family / Base Number Nexperia - 33AC1189 - Newark, An Avnet Company
Chicago, IL, United States
D Flip Flop, Octal, 4.2Ns, Tssop-20; Logic Family / Base Number Nexperia
33AC1189
D Flip Flop, Octal, 4.2Ns, Tssop-20; Logic Family / Base Number Nexperia 33AC1189
D FLIP FLOP, OCTAL, 4.2NS, TSSOP-20; Logic Family / Base Number:74AHC273; Flip-Flop Type:D; Propagation Delay:4.2ns; Frequency:165MHz; Output Current:25mA; Logic Case Style:TSSOP; No. of Pins:20Pins; Trigger Type:Positive Edge; IC RoHS Compliant: Yes

D FLIP FLOP, OCTAL, 4.2NS, TSSOP-20; Logic Family / Base Number:74AHC273; Flip-Flop Type:D; Propagation Delay:4.2ns; Frequency:165MHz; Output Current:25mA; Logic Case Style:TSSOP; No. of Pins:20Pins; Trigger Type:Positive Edge; IC RoHS Compliant: Yes

Supplier's Site
Flip Flops - 74AHC273PW,118 - Quarktwin Technology Ltd.
Shenzhen, Guangdong, China
Flip Flops
74AHC273PW,118
Flip Flops 74AHC273PW,118
Flip Flop 1 Element D-Type 8 Bit Positive Edge 20-TSSOP (0.173", 4.40mm Width)

Flip Flop 1 Element D-Type 8 Bit Positive Edge 20-TSSOP (0.173", 4.40mm Width)

Buy Now Datasheet

Technical Specifications

  Nexperia B.V. Rochester Electronics Win Source Electronics DigiKey Lingto Electronic Limited Newark, An Avnet Company Quarktwin Technology Ltd.
Product Category Flip-Flops Flip-Flops Flip-Flops Flip-Flops Flip-Flops Flip-Flops Flip-Flops
Product Number 74AHC273PW,118 74AHC273PW,118 1007487-74AHC273PW,118 1727-1966-2-ND 74AHC273PW,118 33AC1189 74AHC273PW,118
Product Name Octal D-type flip-flop with reset; positive-edge trigger Logic - Logic - Flip Flops - 74AHC273PW,118 Flip Flops Logic - Flip Flops D Flip Flop, Octal, 4.2Ns, Tssop-20; Logic Family / Base Number Nexperia Flip Flops
Flip-Flop Type D D D
Triggering Positive-edge Triggered Positive-edge Triggered Positive-edge Triggered; Positive Edge Positive-edge Triggered
Supply Voltage +7.0 2 V ~ 5.5 V 2V ~ 5.5V 2V ~ 5.5V
Features ESD Protection
Package Type SOT360-1 SOT360-1 SOT360 TSSOP; "20-TSSOP (0.173"", 4.40mm Width)" TSSOP; TSSOP TSSOP; 20-TSSOP (0.173\", 4.40mm Width); SOP; SSOP
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