The ZL30155 Dual Channel Universal Clock Translator, part of Microchip's ClockCenter platform of Synchronous Clock devices, delivers industry leading synchronization performance for high-speed complex applications. The highly integrated and programmable solution provides translation from any input reference frequency to any output clock frequency with jitter performance that can directly drive 10 G PHY devices. The ZL30155 integrates 2 independent digital PLLs, accepts 4 input references and generates 12 programmable clock outputs. The highly integrated solution allows designers to replace multiple components with a single chip, simplifying design and reducing component count and power.
Additional Features
Two independent clock channels
Programmable synthesizers generate any clock-rate from 1 kHz to 720 MHz
Two precision synthesizers generate clocks with jitter below 0.7ps RMS for 10 G PHYs
Programmable digital PLLs synchronize to any clock rate from 1 kHz to 720 MHz
Flexible two-stage architecture translates between arbitrary data rates, line coding rates and FEC rates
Digital PLLs filter jitter from 14 Hz, 28 Hz, 56 Hz, 112 Hz, 224 Hz, 448 Hz or 896 Hz
Automatic hitless reference switching and digital holdover on reference fail
Four reference inputs configurable as single ended or differential
Eight LVPECL outputs and four LVCMOS outputs
Operates from a single crystal resonator or clock oscillator
Customer defined default configuration, including input/output frequencies, is available via OTP (One Time Programmable) memory
Configurable via SPI/I2C interface
Applications/Uses
- 10 Gigabit linecards
- Synchronous Ethernet, 10GBASE-R and 10GBASE-W
- OTN multiplexers and transponders
- SONET/SDH, Fibre Channel, XAUI
The ZL30155 Dual Channel Universal Clock Translator, part of Microchip's ClockCenter platform of Synchronous Clock devices, delivers industry leading synchronization performance for high-speed complex applications. The highly integrated and programmable solution provides translation from any input reference frequency to any output clock frequency with jitter performance that can directly drive 10 G PHY devices.
The ZL30155 integrates 2 independent digital PLLs, accepts 4 input references and generates 12 programmable clock outputs. The highly integrated solution allows designers to replace multiple components with a single chip, simplifying design and reducing component count and power.
Additional Features
- Two independent clock channels
- Programmable synthesizers generate any clock-rate from 1 kHz to 720 MHz
- Two precision synthesizers generate clocks with jitter below 0.7ps RMS for 10 G PHYs
- Programmable digital PLLs synchronize to any clock rate from 1 kHz to 720 MHz
- Flexible two-stage architecture translates between arbitrary data rates, line coding rates and FEC rates
- Digital PLLs filter jitter from 14 Hz, 28 Hz, 56 Hz, 112 Hz, 224 Hz, 448 Hz or 896 Hz
- Automatic hitless reference switching and digital holdover on reference fail
- Four reference inputs configurable as single ended or differential
- Eight LVPECL outputs and four LVCMOS outputs
- Operates from a single crystal resonator or clock oscillator
- Customer defined default configuration, including input/output frequencies, is available via OTP (One Time Programmable) memory
- Configurable via SPI/I2C interface
- Applications/Uses
- - 10 Gigabit linecards
- - Synchronous Ethernet, 10GBASE-R and 10GBASE-W
- - OTN multiplexers and transponders
- - SONET/SDH, Fibre Channel, XAUI
