Silicon Labs' family of low jitter non-PLL based fanout buffers produce multiple copies of an input clock at the same frequency with minimal additive jitter. LVDS, LVPECL, HCSL, LVCMOS, SSTL and HSTL buffers are available, including devices that support integrated level translation.
The Si5330 devices are ideal for general purpose clock distribution of differential and single-ended signal formats.
The SL18860 TCXO fanout buffer is used to replicate the RF output of the TCXO used in handheld applications like smart phones, GPS navigation devices and tablet computers. Low power (2.7 mA typ), small size 10-TDFN (1.4 mm x 2.0 mm x 0.75 mm) and very low phase noise (-168 dBc @ 1 MHz) make these devices ideal for handheld applications.
Features:
Family supports fanout of 2, 4 or 8
Some devices are spec compatible to Intel’s DB400 and DB800
Individual OEs for each output
Output polarity inversion option
I2C interface available for output control, AC tuning and enable/disable
Silicon Labs' family of low jitter non-PLL based fanout buffers produce multiple copies of an input clock at the same frequency with minimal additive jitter. LVDS, LVPECL, HCSL, LVCMOS, SSTL and HSTL buffers are available, including devices that support integrated level translation.
The Si5330 devices are ideal for general purpose clock distribution of differential and single-ended signal formats.
The SL18860 TCXO fanout buffer is used to replicate the RF output of the TCXO used in handheld applications like smart phones, GPS navigation devices and tablet computers. Low power (2.7 mA typ), small size 10-TDFN (1.4 mm x 2.0 mm x 0.75 mm) and very low phase noise (-168 dBc @ 1 MHz) make these devices ideal for handheld applications.
Features:
- Family supports fanout of 2, 4 or 8
- Some devices are spec compatible to Intel’s DB400 and DB800
- Individual OEs for each output
- Output polarity inversion option
- I2C interface available for output control, AC tuning and enable/disable
