Silicon Labs 4-PLL Jitter Attenuating Clock Si5374

The Si5374/75 any-frequency jitter attenuating clocks integrate four independent jitter attenuating PLLs into a single device, providing industry-leading integration for space-constrained OTN (OTU1, OTU2, OTU3, OTU4) applications. The Si537x can generate any output frequency (2 kHz to 808 MHz) from any input frequency (2 kHz to 710 MHz) with industry-leading jitter performance (0.4 ps rms phase jitter). Silicon Labs’ innovative DSPLL® technology provides any-frequency synthesis and jitter attenuation in a highly integrated PLL solution: Eliminates the need for external VCXO and loop filter components Minimizes BOM cost and complexity Simplifies layout and improving immunity to board-level noise Features: Ultra low jitter generation: 0.4 ps rms phase jitter (12 kHz to 20 MHz) Any-frequency synthesis Digitally programmable loop bandwidth provides application-specific noise filtering (4 Hz to 8 kHz) Meets G.8251 and OC-192 GR-253-CORE jitter specifications Hitless switching w/integrated phase buildout Manual or automatic (revertive, non-revertive) input clock selection Synchronous and/or free-run operation 8 clock inputs 8 differential clock outputs Accepts gapped clock inputs Loss of lock, loss of signal alarms User-selectable output clock signal format: LVPECL, LVDS, CML, CMOS I2C programmable On-chip voltage regulator with high PSRR Pb-free, RoHS-compliant Single supply operating at 1.8 or 2.5 V Small size (10 mm x 10 mm 80-pin BGA)