The 82C50A Asynchronous Communication Element (ACE) is a high performance programmable Universal Asynchronous Receiver/Transmitter (UART) and Baud Rate Generator (BRG) on a single chip. Using Intersil's advanced Scaled SAJI IV CMOS Process, the ACE will support data rates from DC to 625K baud (0-10MHz clock). The ACE's receiver circuitry converts start, data, stop, and parity bits into a parallel data word. The transmitter circuitry converts a parallel data word into serial form and appends the start, parity, and stop bits. The word length is programmable to 5, 6, 7, or 8 data bits. Stop bit selection provides a choice of 1,1.5, or 2 stop bits.brbr The Baud Rate Generator divides the clock by a divisor programmable from 1 to 2sup16/sup-1 to provide standard RS- 232C baud rates when using any one of three industry standard baud rate crystals (1.8432MHz, 2.4576MHz, or 3.072MHz). A programmable buffered clock output (BAUDOUT) provides either a buffered oscillator or 16X (16 times the data rate) baud rate clock for general purpose system use.brbr To meet the system requirements of a CPU interfacing to an asynchronous channel, the modem control signals span style="text-decorati
on: overline"RTS/span, span style="text-decorati
on: overline"CTS/span, span style="text-decorati
on: overline"DSR/span, span style="text-decorati
on: overline"DTR/span, span style="text-decorati
on: overline"RI/span, span style="text-decorati
on: overline"DCD/span are provided. Inputs and outputs have been designed with full TTL/CMOS compatibility in order to facilitate mixed TTL/NMOS/CMOS system design.
The 82C50A Asynchronous Communication Element (ACE) is a high performance programmable Universal Asynchronous Receiver/Transmitter (UART) and Baud Rate Generator (BRG) on a single chip. Using Intersil's advanced Scaled SAJI IV CMOS Process, the ACE will support data rates from DC to 625K baud (0-10MHz clock). The ACE's receiver circuitry converts start, data, stop, and parity bits into a parallel data word. The transmitter circuitry converts a parallel data word into serial form and appends the start, parity, and stop bits. The word length is programmable to 5, 6, 7, or 8 data bits. Stop bit selection provides a choice of 1,1.5, or 2 stop bits.brbr The Baud Rate Generator divides the clock by a divisor programmable from 1 to 2sup16/sup-1 to provide standard RS- 232C baud rates when using any one of three industry standard baud rate crystals (1.8432MHz, 2.4576MHz, or 3.072MHz). A programmable buffered clock output (BAUDOUT) provides either a buffered oscillator or 16X (16 times the data rate) baud rate clock for general purpose system use.brbr To meet the system requirements of a CPU interfacing to an asynchronous channel, the modem control signals span style="text-decoration: overline"RTS/span, span style="text-decoration: overline"CTS/span, span style="text-decoration: overline"DSR/span, span style="text-decoration: overline"DTR/span, span style="text-decoration: overline"RI/span, span style="text-decoration: overline"DCD/span are provided. Inputs and outputs have been designed with full TTL/CMOS compatibility in order to facilitate mixed TTL/NMOS/CMOS system design.
