onsemi Interface - Interface - Controllers - SCANPSC100FSCX SCANPSC100FSCX

The SCANPSC100FSCX is an embedded boundary scan controller designed to interface a generic parallel processor bus with a serial scan test bus, supporting IEEE 1149.1 (JTAG) standards. It enhances scan throughput by serializing data from the parallel bus for efficient application to system test circuitry, while minimizing software overhead. The controller can manage up to two independent scan chains and utilizes user-specific patterns, making it protocol-independent. Key features include a 32-bit counter for programming test clock cycles, support for TCK frequencies up to 25 MHz, and TTL-compatible inputs with full-swing CMOS outputs capable of sourcing or sinking 24 mA. The device is fabricated using a 1.5 µm CMOS process and is compatible with a wide range of processors and clock frequencies. The SCANPSC100FSCX is packaged in a 28-lead Small Outline Integrated Circuit (SOIC) format, suitable for various applications requiring boundary scan testing.