Nexperia B.V. Single D-type flip-flop with set and reset; positive edge trigger 74LVC2G74DP,125

Description
The 74LVC2G74 is a single positive edge triggered D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs, and complementary Q and Q outputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the Q output. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. Features and benefits Wide supply voltage range from 1.65 V to 5.5 V Overvoltage tolerant inputs to 5.5 V High noise immunity Complies with JEDEC standard: JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8-B/JESD36 (2.7 V to 3.6 V) ±24 mA output drive (VCC = 3.0 V) CMOS low power consumption Latch-up performance exceeds 250 mA Direct interface with TTL levels IOFF circuitry provides partial Power-down mode operation ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V Multiple package options Specified from -40 °C to +85 °C and -40 °C to +125 °C
  • Single D-type flip-flop with set and reset; positive edge trigger - 74LVC2G74DP,125 - Nexperia B.V.
    Nexperia B.V.
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Request a Quote Datasheet
Description
The 74LVC2G74 is a single positive edge triggered D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs, and complementary Q and Q outputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the Q output. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. Features and benefits Wide supply voltage range from 1.65 V to 5.5 V Overvoltage tolerant inputs to 5.5 V High noise immunity Complies with JEDEC standard: JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8-B/JESD36 (2.7 V to 3.6 V) ±24 mA output drive (VCC = 3.0 V) CMOS low power consumption Latch-up performance exceeds 250 mA Direct interface with TTL levels IOFF circuitry provides partial Power-down mode operation ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V Multiple package options Specified from -40 °C to +85 °C and -40 °C to +125 °C
Request a Quote Datasheet

Suppliers

Company
Product
Description
Supplier Links
Single D-type flip-flop with set and reset; positive edge trigger - 74LVC2G74DP,125 - Nexperia B.V.
Nexperia B.V.
Nijmegen, Netherlands
Single D-type flip-flop with set and reset; positive edge trigger
74LVC2G74DP,125
Single D-type flip-flop with set and reset; positive edge trigger 74LVC2G74DP,125
The 74LVC2G74 is a single positive edge triggered D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs, and complementary Q and Q outputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the Q output. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. Features and benefits Wide supply voltage range from 1.65 V to 5.5 V Overvoltage tolerant inputs to 5.5 V High noise immunity Complies with JEDEC standard: JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8-B/JESD36 (2.7 V to 3.6 V) ±24 mA output drive (VCC = 3.0 V) CMOS low power consumption Latch-up performance exceeds 250 mA Direct interface with TTL levels IOFF circuitry provides partial Power-down mode operation ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V Multiple package options Specified from -40 °C to +85 °C and -40 °C to +125 °C

The 74LVC2G74 is a single positive edge triggered D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs, and complementary Q and Q outputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the Q output. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments.

Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.

This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

Features and benefits

  • Wide supply voltage range from 1.65 V to 5.5 V
  • Overvoltage tolerant inputs to 5.5 V
  • High noise immunity
  • Complies with JEDEC standard:
    • JESD8-7 (1.65 V to 1.95 V)
    • JESD8-5 (2.3 V to 2.7 V)
    • JESD8-B/JESD36 (2.7 V to 3.6 V)
  • ±24 mA output drive (VCC = 3.0 V)
  • CMOS low power consumption
  • Latch-up performance exceeds 250 mA
  • Direct interface with TTL levels
  • IOFF circuitry provides partial Power-down mode operation
  • ESD protection:
    • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
  • Multiple package options
  • Specified from -40 °C to +85 °C and -40 °C to +125 °C
Supplier's Site Datasheet
Flip Flops - 1727-5994-2-ND - DigiKey
DigiKey
Thief River Falls, MN, United States
Flip Flops
1727-5994-2-ND
Flip Flops 1727-5994-2-ND
"Flip Flop 1 Element D-Type 1 Bit Positive Edge 8-TSSOP, 8-MSOP (0.118"", 3.00mm Width)"

"Flip Flop 1 Element D-Type 1 Bit Positive Edge 8-TSSOP, 8-MSOP (0.118"", 3.00mm Width)"

Buy Now Datasheet
Flip Flops - 1727-5994-1-ND - DigiKey
DigiKey
Thief River Falls, MN, United States
Flip Flops
1727-5994-1-ND
Flip Flops 1727-5994-1-ND
"Flip Flop 1 Element D-Type 1 Bit Positive Edge 8-TSSOP, 8-MSOP (0.118"", 3.00mm Width)"

"Flip Flop 1 Element D-Type 1 Bit Positive Edge 8-TSSOP, 8-MSOP (0.118"", 3.00mm Width)"

Buy Now Datasheet
Flip Flops - 1727-5994-6-ND - DigiKey
DigiKey
Thief River Falls, MN, United States
Flip Flops
1727-5994-6-ND
Flip Flops 1727-5994-6-ND
"Flip Flop 1 Element D-Type 1 Bit Positive Edge 8-TSSOP, 8-MSOP (0.118"", 3.00mm Width)"

"Flip Flop 1 Element D-Type 1 Bit Positive Edge 8-TSSOP, 8-MSOP (0.118"", 3.00mm Width)"

Buy Now Datasheet
Win Source Electronics
Laguna Hills, CA, United States
Logic - Logic - Flip Flops - 74LVC2G74DP,125
1009419-74LVC2G74DP,125
Logic - Logic - Flip Flops - 74LVC2G74DP,125 1009419-74LVC2G74DP,125
Manufacturer: Nexperia USA Inc. Win Source Part Number: 1009419-74LVC2G74DP, 125 Packaging: Reel - TR Type: D-Type Mounting: SMD (SMT) Output Type: Differential Current - Output High, Low: 32mA, 32mA Number of Elements: 1 Number of Bits per Element: 1 Max Propagation Delay @ V, Max CL: 4.1ns @ 5V, 50pF Trigger Type: Positive Edge Current - Quiescent: 40μA Input Capacitance: 4pF Categories: Integrated Circuits Status: Active Temperature Range - Operating: -40°C to 125°C (TA) Dimension: 8-TSSOP, 8-MSOP (0.118", 3.00mm Width) Purpose: Set(Preset) and Reset Supply Voltage - Operating: 1.65 V to 5.5 V Max Frequency: 200MHz Popularity: Medium Fake Threat In the Open Market: 68 pct. Supply and Demand Status: Sufficient

Manufacturer: Nexperia USA Inc.
Win Source Part Number: 1009419-74LVC2G74DP,125
Packaging: Reel - TR
Type: D-Type
Mounting: SMD (SMT)
Output Type: Differential
Current - Output High, Low: 32mA, 32mA
Number of Elements: 1
Number of Bits per Element: 1
Max Propagation Delay @ V, Max CL: 4.1ns @ 5V, 50pF
Trigger Type: Positive Edge
Current - Quiescent: 40μA
Input Capacitance: 4pF
Categories: Integrated Circuits
Status: Active
Temperature Range - Operating: -40°C to 125°C (TA)
Dimension: 8-TSSOP, 8-MSOP (0.118", 3.00mm Width)
Purpose: Set(Preset) and Reset
Supply Voltage - Operating: 1.65 V to 5.5 V
Max Frequency: 200MHz
Popularity: Medium
Fake Threat In the Open Market: 68 pct.
Supply and Demand Status: Sufficient

Buy Now Datasheet
- 74LVC2G74DP,125 - Rochester Electronics
Rochester Electronics
Newburyport, MA, United States
74LVC2G74DP,125
74LVC2G74DP,125
D Flip-Flop, LVC/LCX/Z Series, 1-Func, Positive Edge Triggered, 1-Bit, Complementary Output, CMOS, PDSO8

D Flip-Flop, LVC/LCX/Z Series, 1-Func, Positive Edge Triggered, 1-Bit, Complementary Output, CMOS, PDSO8

Supplier's Site Datasheet
Flip-Flop, D-Type, 200Mhz, Tssop-8; Logic Family / Base Number Nexperia - 93X4967 - Newark, An Avnet Company
Newark, An Avnet Company
Chicago, IL, United States
Flip-Flop, D-Type, 200Mhz, Tssop-8; Logic Family / Base Number Nexperia
93X4967
Flip-Flop, D-Type, 200Mhz, Tssop-8; Logic Family / Base Number Nexperia 93X4967
FLIP-FLOP, D-TYPE, 200MHZ, TSSOP-8; Logic Family / Base Number:74LVC74; Flip-Flop Type:D; Propagation Delay:-; Frequency:200MHz; Output Current:50mA; Logic Case Style:TSSOP; No. of Pins:8Pins; Trigger Type:Positive Edge; IC Output RoHS Compliant: Yes

FLIP-FLOP, D-TYPE, 200MHZ, TSSOP-8; Logic Family / Base Number:74LVC74; Flip-Flop Type:D; Propagation Delay:-; Frequency:200MHz; Output Current:50mA; Logic Case Style:TSSOP; No. of Pins:8Pins; Trigger Type:Positive Edge; IC Output RoHS Compliant: Yes

Supplier's Site Datasheet
Flip-Flop, D-Type, 200Mhz, Tssop-8; Logic Family / Base Number Nexperia - 04AJ5941 - Newark, An Avnet Company
Newark, An Avnet Company
Chicago, IL, United States
Flip-Flop, D-Type, 200Mhz, Tssop-8; Logic Family / Base Number Nexperia
04AJ5941
Flip-Flop, D-Type, 200Mhz, Tssop-8; Logic Family / Base Number Nexperia 04AJ5941
FLIP-FLOP, D-TYPE, 200MHZ, TSSOP-8; Logic Family / Base Number:74LVC74; Flip-Flop Type:D; Propagation Delay:-; Frequency:200MHz; Output Current:50mA; Logic Case Style:TSSOP; No. of Pins:8Pins; Trigger Type:Positive Edge; IC Output RoHS Compliant: Yes

FLIP-FLOP, D-TYPE, 200MHZ, TSSOP-8; Logic Family / Base Number:74LVC74; Flip-Flop Type:D; Propagation Delay:-; Frequency:200MHz; Output Current:50mA; Logic Case Style:TSSOP; No. of Pins:8Pins; Trigger Type:Positive Edge; IC Output RoHS Compliant: Yes

Supplier's Site Datasheet
Integrated Circuits (ICs) - Logic - Flip Flops - 74LVC2G74DP,125 - Shenzhen Shengyu Electronics Technology Limited
Shenzhen Shengyu Electronics Technology Limited
Futian, China
Integrated Circuits (ICs) - Logic - Flip Flops
74LVC2G74DP,125
Integrated Circuits (ICs) - Logic - Flip Flops 74LVC2G74DP,125
IC FF D-TYPE SNGL 1BIT 8TSSOP

IC FF D-TYPE SNGL 1BIT 8TSSOP

Supplier's Site
LCSC Electronics Technology (HK) Limited
Futian, Shenzhen, China
Logic ICs >> Flip Flops
74LVC2G74DP,125
Logic ICs >> Flip Flops 74LVC2G74DP,125
1.65V~5.5V 200MHz 4.1ns@5V,50pF D-Type 1 1 40uA TSSOP-8 Flip Flops ROHS

1.65V~5.5V 200MHz 4.1ns@5V,50pF D-Type 1 1 40uA TSSOP-8 Flip Flops ROHS

Supplier's Site Datasheet
Flip Flops - 74LVC2G74DP,125 - Quarktwin Technology Ltd.
Quarktwin Technology Ltd.
Shenzhen, Guangdong, China
Flip Flops
74LVC2G74DP,125
Flip Flops 74LVC2G74DP,125
Flip Flop 1 Element D-Type 1 Bit Positive Edge 8-TSSOP, 8-MSOP (0.118", 3.00mm Width)

Flip Flop 1 Element D-Type 1 Bit Positive Edge 8-TSSOP, 8-MSOP (0.118", 3.00mm Width)

Buy Now Datasheet
74LVC Series 5.5 V Positive Edge Trigger D-Type Flip-Flop Surface Mount -TSSOP-8 - 554-74LVC2G74DP,125 - Utmel Electronic Limited
Utmel Electronic Limited
Hong Kong, China
74LVC Series 5.5 V Positive Edge Trigger D-Type Flip-Flop Surface Mount -TSSOP-8
554-74LVC2G74DP,125
74LVC Series 5.5 V Positive Edge Trigger D-Type Flip-Flop Surface Mount -TSSOP-8 554-74LVC2G74DP,125
74LVC Series 5.5 V Positive Edge Trigger D-Type Flip-Flop Surface Mount -TSSOP-8

74LVC Series 5.5 V Positive Edge Trigger D-Type Flip-Flop Surface Mount -TSSOP-8

Supplier's Site
Logic - Flip Flops - 74LVC2G74DP,125 - Lingto Electronic Limited
Lingto Electronic Limited
Shenzhen, China
Logic - Flip Flops
74LVC2G74DP,125
Logic - Flip Flops 74LVC2G74DP,125
IC FF D-TYPE SNGL 1BIT 8TSSOP

IC FF D-TYPE SNGL 1BIT 8TSSOP

Supplier's Site Datasheet

Technical Specifications

  Nexperia B.V. DigiKey Win Source Electronics Rochester Electronics Newark, An Avnet Company Shenzhen Shengyu Electronics Technology Limited LCSC Electronics Technology (HK) Limited Quarktwin Technology Ltd. Utmel Electronic Limited Lingto Electronic Limited
Product Category Flip-Flops Flip-Flops Flip-Flops Flip-Flops Flip-Flops Flip-Flops Flip-Flops Flip-Flops Flip-Flops Flip-Flops
Product Number 74LVC2G74DP,125 1727-5994-2-ND 1009419-74LVC2G74DP,125 74LVC2G74DP,125 93X4967 74LVC2G74DP,125 74LVC2G74DP,125 74LVC2G74DP,125 554-74LVC2G74DP,125 74LVC2G74DP,125
Product Name Single D-type flip-flop with set and reset; positive edge trigger Flip Flops Logic - Logic - Flip Flops - 74LVC2G74DP,125 Flip-Flop, D-Type, 200Mhz, Tssop-8; Logic Family / Base Number Nexperia Integrated Circuits (ICs) - Logic - Flip Flops Logic ICs >> Flip Flops Flip Flops 74LVC Series 5.5 V Positive Edge Trigger D-Type Flip-Flop Surface Mount -TSSOP-8 Logic - Flip Flops
Flip-Flop Type D D D D D
Triggering Positive-edge Triggered Positive-edge Triggered Positive-edge Triggered; Positive Edge Positive-edge Triggered Positive-edge Triggered
Supply Voltage 1.8V; 2.5V; 3V; 3.3V; 3.6V; 5V; 1.65 - 5.5 1.65V ~ 5.5V 1.65 V ~ 5.5 V 1.65V~5.5V 1.65V ~ 5.5V 1.8V
Features ESD Protection
Propagation Delay 3.5 ns 4.1 ns 4.1 ns 4.1 ns 4.1 ns
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