Nexperia B.V. Dual 2-input NOR gate 74LVC2G02GN,115

Description
The 74LVC2G02 is a dual 2-input NOR gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. Features and benefits Wide supply voltage range from 1.65 V to 5.5 V 5 V tolerant outputs for interfacing with 5 V logic Overvoltage tolerant inputs to 5.5 V High noise immunity ±24 mA output drive (VCC = 3.0 V) CMOS low power consumption IOFF circuitry provides partial Power-down mode operation Latch-up performance exceeds 250 mA Direct interface with TTL levels Complies with JEDEC standard: JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8-B/JESD36 (2.7 V to 3.6 V) ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V Multiple package options Specified from -40 °C to +85 °C and -40 °C to +125 °C
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Description
The 74LVC2G02 is a dual 2-input NOR gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. Features and benefits Wide supply voltage range from 1.65 V to 5.5 V 5 V tolerant outputs for interfacing with 5 V logic Overvoltage tolerant inputs to 5.5 V High noise immunity ±24 mA output drive (VCC = 3.0 V) CMOS low power consumption IOFF circuitry provides partial Power-down mode operation Latch-up performance exceeds 250 mA Direct interface with TTL levels Complies with JEDEC standard: JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8-B/JESD36 (2.7 V to 3.6 V) ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V Multiple package options Specified from -40 °C to +85 °C and -40 °C to +125 °C
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Suppliers

Company
Product
Description
Supplier Links
Dual 2-input NOR gate - 74LVC2G02GN,115 - Nexperia B.V.
Nijmegen, Netherlands
Dual 2-input NOR gate
74LVC2G02GN,115
Dual 2-input NOR gate 74LVC2G02GN,115
The 74LVC2G02 is a dual 2-input NOR gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. Features and benefits Wide supply voltage range from 1.65 V to 5.5 V 5 V tolerant outputs for interfacing with 5 V logic Overvoltage tolerant inputs to 5.5 V High noise immunity ±24 mA output drive (VCC = 3.0 V) CMOS low power consumption IOFF circuitry provides partial Power-down mode operation Latch-up performance exceeds 250 mA Direct interface with TTL levels Complies with JEDEC standard: JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8-B/JESD36 (2.7 V to 3.6 V) ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V Multiple package options Specified from -40 °C to +85 °C and -40 °C to +125 °C

The 74LVC2G02 is a dual 2-input NOR gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments.

Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.

This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

Features and benefits

  • Wide supply voltage range from 1.65 V to 5.5 V
  • 5 V tolerant outputs for interfacing with 5 V logic
  • Overvoltage tolerant inputs to 5.5 V
  • High noise immunity
  • ±24 mA output drive (VCC = 3.0 V)
  • CMOS low power consumption
  • IOFF circuitry provides partial Power-down mode operation
  • Latch-up performance exceeds 250 mA
  • Direct interface with TTL levels
  • Complies with JEDEC standard:
    • JESD8-7 (1.65 V to 1.95 V)
    • JESD8-5 (2.3 V to 2.7 V)
    • JESD8-B/JESD36 (2.7 V to 3.6 V)
  • ESD protection:
    • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
  • Multiple package options
  • Specified from -40 °C to +85 °C and -40 °C to +125 °C
Supplier's Site Datasheet
Gates and Inverters - 1727-74LVC2G02GN,115CT-ND - DigiKey
Thief River Falls, MN, United States
Gates and Inverters
1727-74LVC2G02GN,115CT-ND
Gates and Inverters 1727-74LVC2G02GN,115CT-ND
IC GATE NOR 2CH 2-INP 8XSON

IC GATE NOR 2CH 2-INP 8XSON

Buy Now Datasheet
Gates and Inverters - 1727-74LVC2G02GN,115DKR-ND - DigiKey
Thief River Falls, MN, United States
Gates and Inverters
1727-74LVC2G02GN,115DKR-ND
Gates and Inverters 1727-74LVC2G02GN,115DKR-ND
IC GATE NOR 2CH 2-INP 8XSON

IC GATE NOR 2CH 2-INP 8XSON

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Gates and Inverters - 1727-74LVC2G02GN,115TR-ND - DigiKey
Thief River Falls, MN, United States
Gates and Inverters
1727-74LVC2G02GN,115TR-ND
Gates and Inverters 1727-74LVC2G02GN,115TR-ND
NOR Gate IC 2 Channel 8-XSON (1.2x1)

NOR Gate IC 2 Channel 8-XSON (1.2x1)

Buy Now Datasheet
 - 74LVC2G02GN,115 - Rochester Electronics
Newburyport, MA, United States
NOR Gate, LVC/LCX/Z Series, 2-Func, 2-Input, CMOS, PDSO8

NOR Gate, LVC/LCX/Z Series, 2-Func, 2-Input, CMOS, PDSO8

Supplier's Site Datasheet
Logic - Gates and Inverters - 74LVC2G02GN,115 - Lingto Electronic Limited
Shenzhen, China
Logic - Gates and Inverters
74LVC2G02GN,115
Logic - Gates and Inverters 74LVC2G02GN,115
IC GATE NOR 2CH 2-INP 8XSON

IC GATE NOR 2CH 2-INP 8XSON

Supplier's Site Datasheet
Gates and Inverters - 74LVC2G02GN,115 - Quarktwin Technology Ltd.
Shenzhen, Guangdong, China
Gates and Inverters
74LVC2G02GN,115
Gates and Inverters 74LVC2G02GN,115
NOR Gate IC 2 Channel 8-XSON (1.2x1)

NOR Gate IC 2 Channel 8-XSON (1.2x1)

Buy Now Datasheet

Technical Specifications

  Nexperia B.V. DigiKey Rochester Electronics Lingto Electronic Limited Quarktwin Technology Ltd.
Product Category Logic Gates Logic Gates Logic Gates Logic Gates Logic Gates
Product Number 74LVC2G02GN,115 1727-74LVC2G02GN,115CT-ND 74LVC2G02GN,115 74LVC2G02GN,115 74LVC2G02GN,115
Product Name Dual 2-input NOR gate Gates and Inverters Logic - Gates and Inverters Gates and Inverters
Gate Type NOR NOR OR; NOR NOT; NOR NOR; NOR Gate
Supply Voltage 1.8V; 2.5V; 3V; 3.3V; 3.6V; 5V; 1.65 - 5.5 1.65V ~ 5.5V 1.7V ~ 2V (Low), 0.7V ~ 0.8V (High) 1.65V ~ 5.5V
Logic Family CMOS/LVTTL CMOS
Propagation Delay 2.4 ns 4.3 ns
Operating Temperature -40 to 125 C (-40 to 257 F) -40 to 125 C (-40 to 257 F) -40 to 125 C (-40 to 257 F)
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