Nexperia B.V. Low-power 2-input NAND gate 74AUP1G00GN,132

Description
The 74AUP1G00 is a single 2-input NAND gate. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. Features and benefits Wide supply voltage range from 0.8 V to 3.6 V CMOS low power dissipation High noise immunity Complies with JEDEC standards: JESD8-12 (0.8 V to 1.3 V) JESD8-11 (0.9 V to 1.65 V) JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8C (2.7 V to 3.6 V) Low static power consumption; ICC = 0.9 μA (maximum) Latch-up performance exceeds 100 mA per JESD 78 Class II Overvoltage tolerant inputs to 3.6 V Low noise overshoot and undershoot < 10 % of VCC IOFF circuitry provides partial Power-down mode operation Multiple package options ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V Specified from -40 °C to +85 °C and -40 °C to +125 °C
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Suppliers

Company
Product
Description
Supplier Links
Low-power 2-input NAND gate - 74AUP1G00GN,132 - Nexperia B.V.
Nijmegen, Netherlands
Low-power 2-input NAND gate
74AUP1G00GN,132
Low-power 2-input NAND gate 74AUP1G00GN,132
The 74AUP1G00 is a single 2-input NAND gate. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. Features and benefits Wide supply voltage range from 0.8 V to 3.6 V CMOS low power dissipation High noise immunity Complies with JEDEC standards: JESD8-12 (0.8 V to 1.3 V) JESD8-11 (0.9 V to 1.65 V) JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8C (2.7 V to 3.6 V) Low static power consumption; ICC = 0.9 μA (maximum) Latch-up performance exceeds 100 mA per JESD 78 Class II Overvoltage tolerant inputs to 3.6 V Low noise overshoot and undershoot < 10 % of VCC IOFF circuitry provides partial Power-down mode operation Multiple package options ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V Specified from -40 °C to +85 °C and -40 °C to +125 °C

The 74AUP1G00 is a single 2-input NAND gate. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.

Features and benefits

  • Wide supply voltage range from 0.8 V to 3.6 V
  • CMOS low power dissipation
  • High noise immunity
  • Complies with JEDEC standards:
    • JESD8-12 (0.8 V to 1.3 V)
    • JESD8-11 (0.9 V to 1.65 V)
    • JESD8-7 (1.65 V to 1.95 V)
    • JESD8-5 (2.3 V to 2.7 V)
    • JESD8C (2.7 V to 3.6 V)
  • Low static power consumption; ICC = 0.9 μA (maximum)
  • Latch-up performance exceeds 100 mA per JESD 78 Class II
  • Overvoltage tolerant inputs to 3.6 V
  • Low noise overshoot and undershoot < 10 % of VCC
  • IOFF circuitry provides partial Power-down mode operation
  • Multiple package options
  • ESD protection:
    • HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V
    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
  • Specified from -40 °C to +85 °C and -40 °C to +125 °C
Supplier's Site Datasheet
Gates and Inverters - 74AUP1G00GN,132 - Quarktwin Technology Ltd.
Shenzhen, Guangdong, China
Gates and Inverters
74AUP1G00GN,132
Gates and Inverters 74AUP1G00GN,132
IC Channel

IC Channel

Supplier's Site Datasheet
Gates and Inverters - 74AUP1G00GN,132 - Quarktwin Technology Ltd.
Shenzhen, Guangdong, China
Gates and Inverters
74AUP1G00GN,132
Gates and Inverters 74AUP1G00GN,132
NAND Gate IC 1 Channel 6-XSON (0.9x1)

NAND Gate IC 1 Channel 6-XSON (0.9x1)

Supplier's Site Datasheet
Gates and Inverters - 1727-74AUP1G00GN,132DKR-ND - DigiKey
Thief River Falls, MN, United States
Gates and Inverters
1727-74AUP1G00GN,132DKR-ND
Gates and Inverters 1727-74AUP1G00GN,132DKR-ND
NAND Gate IC 1 Channel 6-XSON (0.9x1)

NAND Gate IC 1 Channel 6-XSON (0.9x1)

Supplier's Site Datasheet
Gates and Inverters - 1727-74AUP1G00GN,132CT-ND - DigiKey
Thief River Falls, MN, United States
Gates and Inverters
1727-74AUP1G00GN,132CT-ND
Gates and Inverters 1727-74AUP1G00GN,132CT-ND
NAND Gate IC 1 Channel 6-XSON (0.9x1)

NAND Gate IC 1 Channel 6-XSON (0.9x1)

Supplier's Site Datasheet
Gates and Inverters - 1727-74AUP1G00GN,132TR-ND - DigiKey
Thief River Falls, MN, United States
Gates and Inverters
1727-74AUP1G00GN,132TR-ND
Gates and Inverters 1727-74AUP1G00GN,132TR-ND
NAND Gate IC 1 Channel 6-XSON (0.9x1)

NAND Gate IC 1 Channel 6-XSON (0.9x1)

Supplier's Site Datasheet
Integrated Circuits (ICs) - Logic - Gates and Inverters - 74AUP1G00GN,132 - Shenzhen Shengyu Electronics Technology Limited
Futian, China
Integrated Circuits (ICs) - Logic - Gates and Inverters
74AUP1G00GN,132
Integrated Circuits (ICs) - Logic - Gates and Inverters 74AUP1G00GN,132
IC GATE NAND 1CH 2-INP 6XSON

IC GATE NAND 1CH 2-INP 6XSON

Supplier's Site
Logic - Gates and Inverters - 74AUP1G00GN,132 - Lingto Electronic Limited
Shenzhen, China
Logic - Gates and Inverters
74AUP1G00GN,132
Logic - Gates and Inverters 74AUP1G00GN,132
IC GATE NAND 1CH 2-INP 6XSON

IC GATE NAND 1CH 2-INP 6XSON

Supplier's Site Datasheet
 - 74AUP1G00GN,132 - Rochester Electronics
Newburyport, MA, United States
Nexperia 74AUP1G00GN - NAND Gate, AUP/ULP/V Series, 1-Func, 2-Input, CMOS, X2SON6

Nexperia 74AUP1G00GN - NAND Gate, AUP/ULP/V Series, 1-Func, 2-Input, CMOS, X2SON6

Supplier's Site Datasheet

Technical Specifications

  Nexperia B.V. Quarktwin Technology Ltd. Quarktwin Technology Ltd. DigiKey Shenzhen Shengyu Electronics Technology Limited Lingto Electronic Limited Rochester Electronics
Product Category Logic Gates Logic Gates Logic Gates Logic Gates Logic Gates Logic Gates Logic Gates
Product Number 74AUP1G00GN,132 74AUP1G00GN,132 74AUP1G00GN,132 1727-74AUP1G00GN,132DKR-ND 74AUP1G00GN,132 74AUP1G00GN,132 74AUP1G00GN,132
Product Name Low-power 2-input NAND gate Gates and Inverters Gates and Inverters Gates and Inverters Integrated Circuits (ICs) - Logic - Gates and Inverters Logic - Gates and Inverters
Gate Type NAND NAND; NAND Gate NAND NAND NOT; NAND AND; NAND
Supply Voltage 0.8 - 3.6 3.6V; 0.8V ~ 3.6V 0.8V ~ 3.6V 3.6V 1.6V ~ 2V (Low), 0.7V ~ 0.9V (High)
Logic Family CMOS CMOS
Propagation Delay 8.3 ns 6.5 ns
Operating Temperature -40 to 125 C (-40 to 257 F) -40 to 125 C (-40 to 257 F) -40 to 125 C (-40 to 257 F)
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