The ZL30603 offers three DPLL channels of Synchronous Ethernet (SyncE) packet clock synchronization. Using Microsemi’s fourth generation timing technology, these devices offer one third the jitter of the previous generation devices and have a 40% smaller footprint. Each device integrates all features required by a timing card PLL and line card PLL. High integration along with ultra-low jitter make these devices ideal for use in chassis based systems with active and redundant timing cards as well as in single board (“pizza box”) applications where a timing device needs to have features of both a timing and a line card PLL.
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Additional Features
Up to three independent clock channels
Fully compliant to EEC (G.8262), SEC (G.813), GR-253 SMC and GR-1244 Stratum 3/3E
Excellent jitter performance of 180 fs RMS in the 12 kHz to 20 MHz band meets jitter requirements for 10G/40G and 100G PHYs
Three programmable ultra-low jitter synthesizers generate any frequency from 0.5 Hz to 900 MHz
One programmable general purpose synthesizer generates any clock from 0.5 Hz to 180 MHz
6 differential (CML) or 12 single ended (CMOS) ultra-low jitter outputs plus two general purpose CMOS outputs
Accepts up to 10 LVPECL/LVDS/HCSL/LVC
MOS inputs
Up to four programmable digital PLLs/NCOs with loop bandwidth from 0.1 mHz to 470 Hz synchronize to any clock rate from 0.5 Hz to 900 MHz
Automatic hitless reference switching and digital holdover on reference fail with initial holdover accuracy better than 0.1 ppb
Any input reference can be fed with clock, sync (frame pulse), clock /sync pair or clock modulated with sync pulse (embedded PPS ePPS and embedded PP2S ePP2S)
Easy Configuration and dynamic programming via SPI/I2C interface
Operates from a single crystal resonator or clock oscillator
The ZL30603 offers three DPLL channels of Synchronous Ethernet (SyncE) packet clock synchronization. Using Microsemi’s fourth generation timing technology, these devices offer one third the jitter of the previous generation devices and have a 40% smaller footprint. Each device integrates all features required by a timing card PLL and line card PLL. High integration along with ultra-low jitter make these devices ideal for use in chassis based systems with active and redundant timing cards as well as in single board (“pizza box”) applications where a timing device needs to have features of both a timing and a line card PLL.
Click here for secure documentation
Additional Features
- Up to three independent clock channels
- Fully compliant to EEC (G.8262), SEC (G.813), GR-253 SMC and GR-1244 Stratum 3/3E
- Excellent jitter performance of 180 fs RMS in the 12 kHz to 20 MHz band meets jitter requirements for 10G/40G and 100G PHYs
- Three programmable ultra-low jitter synthesizers generate any frequency from 0.5 Hz to 900 MHz
- One programmable general purpose synthesizer generates any clock from 0.5 Hz to 180 MHz
- 6 differential (CML) or 12 single ended (CMOS) ultra-low jitter outputs plus two general purpose CMOS outputs
- Accepts up to 10 LVPECL/LVDS/HCSL/LVCMOS inputs
- Up to four programmable digital PLLs/NCOs with loop bandwidth from 0.1 mHz to 470 Hz synchronize to any clock rate from 0.5 Hz to 900 MHz
- Automatic hitless reference switching and digital holdover on reference fail with initial holdover accuracy better than 0.1 ppb
- Any input reference can be fed with clock, sync (frame pulse), clock /sync pair or clock modulated with sync pulse (embedded PPS ePPS and embedded PP2S ePP2S)
- Easy Configuration and dynamic programming via SPI/I2C interface
- Operates from a single crystal resonator or clock oscillator
