The ZL30702 offers two independent timing channels of a combined hardware and software platform including IEEE 1588-2008 Precision Time Protocol Stack and Synchronization Algorithms. This device provides a highly integrated Synchronous Ethernet / IEEE 1588 timing solution with one third the jitter of previous generation devices with a 40% smaller footprint, making these devices ideal for timing card applications in systems that need to support 10G/40G and 100G Phys.
Click here for secured data sheet, application notes, BSDL file, IBIS model and GUI SW
Click here for the list of supported IEEE 1588-2008 PTP Profiles and Equipment Clock Specifications
Additional Features
Up to two independent clock channels
Fully compliant to EEC (G.8262), SEC (G.813), GR-253 SMC and GR-1244 Stratum 3/3E
Frequency accuracy performance for GSM, WCDMAFDD, LTE-FDD basestations and small cell applications, with target performance less than ± 15 ppb
Frequency performance for ITU-T G.823 and G.824 synchronization interface, as well as G.8261 PNT EEC, PNT PEC and CES interface specifications
Phase Synchronization performance for WCDMA-TDD, TD-SCDMA, CDMA2000, LTE-TDD and LTE-A applications with target performance less than ± 1 μs phase alignment
Client holdover and reference switching between multiple Servers
Support for new ITU-T packet clock recommendations or drafts: G.8263 PEC-S, G.8273.2 T-BC, T-TSC, G.8273.4 T-BC-P, T-TSC-P & T-TSC-A
Excellent jitter performance of 180 fs RMS (12 kHz to 20 MHz) meets 10G/40G and 100G PHY jitter requirements
Up to four programmable digital PLLs/NCOs with loop bandwidth from 0.1 mHz to 470 Hz synchronize to any clock rate from 0.5 Hz to 900 MHz
Automatic hitless reference switching and digital holdover on reference fail with initial holdover accuracy better than 0.1 ppb
Any input reference can be fed with clock, sync (frame pulse), clock /sync pair
Easy configuration and dynamic programming via SPI/I2C interface
Operates from a single crystal resonator or clock oscillator
The ZL30702 offers two independent timing channels of a combined hardware and software platform including IEEE 1588-2008 Precision Time Protocol Stack and Synchronization Algorithms. This device provides a highly integrated Synchronous Ethernet / IEEE 1588 timing solution with one third the jitter of previous generation devices with a 40% smaller footprint, making these devices ideal for timing card applications in systems that need to support 10G/40G and 100G Phys.
Click here for secured data sheet, application notes, BSDL file, IBIS model and GUI SW
Click here for the list of supported IEEE 1588-2008 PTP Profiles and Equipment Clock Specifications
Additional Features
- Up to two independent clock channels
- Fully compliant to EEC (G.8262), SEC (G.813), GR-253 SMC and GR-1244 Stratum 3/3E
- Frequency accuracy performance for GSM, WCDMAFDD, LTE-FDD basestations and small cell applications, with target performance less than ± 15 ppb
- Frequency performance for ITU-T G.823 and G.824 synchronization interface, as well as G.8261 PNT EEC, PNT PEC and CES interface specifications
- Phase Synchronization performance for WCDMA-TDD, TD-SCDMA, CDMA2000, LTE-TDD and LTE-A applications with target performance less than ± 1 μs phase alignment
- Client holdover and reference switching between multiple Servers
- Support for new ITU-T packet clock recommendations or drafts: G.8263 PEC-S, G.8273.2 T-BC, T-TSC, G.8273.4 T-BC-P, T-TSC-P & T-TSC-A
- Excellent jitter performance of 180 fs RMS (12 kHz to 20 MHz) meets 10G/40G and 100G PHY jitter requirements
- Up to four programmable digital PLLs/NCOs with loop bandwidth from 0.1 mHz to 470 Hz synchronize to any clock rate from 0.5 Hz to 900 MHz
- Automatic hitless reference switching and digital holdover on reference fail with initial holdover accuracy better than 0.1 ppb
- Any input reference can be fed with clock, sync (frame pulse), clock /sync pair
- Easy configuration and dynamic programming via SPI/I2C interface
- Operates from a single crystal resonator or clock oscillator
