The ZL30281 is a high-performance PCIe Gen 1-4 clock generator. From a 25MHz crystal or CMOS input these devices generate 100 MHZ in four pre-programmed output configurations immediately on power-up. The devices have industry-leading output jitter of 160fs RMS (12kHz to 20MHz).
Additional Features
25MHz crystal or CMOS input
Generates PCIe 1, 2, 3, 4, 5 compliant clocks
Four default configurations selected by hardware pins at reset:
Config0: 100MHz on output OC1 (CML format)
Config1: 100MHz on OC1, OC2 (CML)
Config2: 100MHz on OC1 (CML), OC2 (HSTL)
Config3: 100MHz on OC1, OC2 (CML) and 25MHz LVCMOS on OC3
Per-output controls (using SPI or I2C interface)
Per-output enable/disable and glitch-less start/stop (stop high or low)
Precise output alignment circuitry and per-output phase adjustment
SPI or I2C processor Interface
Tiny 5x5mm QFN package
The ZL30281 is a high-performance PCIe Gen 1-4 clock generator. From a 25MHz crystal or CMOS input these devices generate 100 MHZ in four pre-programmed output configurations immediately on power-up. The
devices have industry-leading output jitter of 160fs RMS (12kHz to 20MHz).
Additional Features
- 25MHz crystal or CMOS input
- Generates PCIe 1, 2, 3, 4, 5 compliant clocks
- Four default configurations selected by hardware pins at reset:
- Config0: 100MHz on output OC1 (CML format)
- Config1: 100MHz on OC1, OC2 (CML)
- Config2: 100MHz on OC1 (CML), OC2 (HSTL)
- Config3: 100MHz on OC1, OC2 (CML) and 25MHz LVCMOS on OC3
- Per-output controls (using SPI or I2C interface)
- Per-output enable/disable and glitch-less start/stop (stop high or low)
- Precise output alignment circuitry and per-output phase adjustment
- SPI or I2C processor Interface
- Tiny 5x5mm QFN package
