The SY100ELT21L is a single differential LVPECL to- LVTTL translator s using a single +3.3V power supply. Because LVPECL (Low Voltage Positive ECL) levels are used, only +3.3V and ground are required. The small outline 8-lead SOIC package and low skew single gate design make the ELT21L ideal for applications that require the translation of a clock or data signal where minimal space, low power, and low cost are critical. VBB allows a differential, single-ended, or AC-coupled interface to the device. If used, the VBB output should be bypassed to VCC with 0.01µF capacitor. Under open input conditions, the /D will be biased at a VCC/2 voltage level and the D input will be pulled to ground. This condition will force the Q output low to provide added stability. The 100ELT is compatible with positive ECL 100K logic levels.
Additional Features
3.3V power supply
2.0ns typical propagation delay
Low power
Differential LVPECL inputs
24mA TTL outputs
Flow-through pinouts
Available in 8-pin SOIC package
The SY100ELT21L is a single differential LVPECL to- LVTTL translator s using a single +3.3V power supply. Because LVPECL (Low Voltage Positive ECL) levels are used, only +3.3V and ground are required. The small outline 8-lead SOIC package and low skew single gate design make the ELT21L ideal for applications that require the translation of a clock or data signal where minimal space, low power, and low cost are critical. VBB allows a differential, single-ended, or AC-coupled interface to the device. If used, the VBB output should be bypassed to VCC with 0.01µF capacitor. Under open input conditions, the /D will be biased at a VCC/2 voltage level and the D input will be pulled to ground. This condition will force the Q output low to provide added stability. The 100ELT is compatible with positive ECL 100K logic levels.
Additional Features
- 3.3V power supply
- 2.0ns typical propagation delay
- Low power
- Differential LVPECL inputs
- 24mA TTL outputs
- Flow-through pinouts
- Available in 8-pin SOIC package
