The SCH5627 is a 3.3V PC 2001 compliant Super I/O controller with an LPC interface. All legacy drivers used for Super I/O components are supported, making this interface transparent to the supporting software. The LPC bus also supports power management, such as wake-up and sleep modes. This device can monitor up to three external diodes, one internal ambient temperature sensor or retrieving temperatures from external processors that implement the PECI (Platform Environmental Control Interface). The Glue Logic includes various power management logic, including generation of RSMRST# and Power OK signal generation. The part also provides a low battery warning circuit, as well as 60 General Purpose I/O control pins, which offer flexibility to the system designer. A high-performance embedded microcontroller incorporated and communication-capabl
e with the system host using the Intel® Low Pin Count bus.
Family parts SCH5627-NS SCH5627P-NS
Additional Features
8042 Keyboard Controller
128 QFP Packaging
60 GPIO Pins
μController Fan Control Engine
PECI 1.1, x2 CPU, x4 domain, C3/C4
PCH Temp Monitoring
AMD SB-TSI
2 SMBus Interfaces (master or slave)
IEEE 1284, EPP, ECP, and IBM PC/AT Compatible Parallel Port
Two 16C550A UART-compatible serial ports
Floppy disk controller
4 PWM Outputs
4 fan tachometer inputs
Programmable automatic fan control support
Bi-directional PROCHOT# pin support
The SCH5627 is a 3.3V PC 2001 compliant Super I/O controller with an LPC interface. All legacy drivers used for Super I/O components are supported, making this interface transparent to the supporting software. The LPC bus also supports power management, such as wake-up and sleep modes.
This device can monitor up to three external diodes, one internal ambient temperature sensor or retrieving temperatures from external processors that
implement the PECI (Platform Environmental Control Interface).
The Glue Logic includes various power management logic, including generation of RSMRST# and Power OK signal generation. The part also provides a low battery warning circuit, as well as 60 General Purpose I/O control pins, which offer flexibility to the system designer. A high-performance embedded microcontroller incorporated and communication-capable with the system host using the Intel® Low Pin Count bus.
Family parts
SCH5627-NS
SCH5627P-NS
Additional Features
- 8042 Keyboard Controller
- 128 QFP Packaging
- 60 GPIO Pins
- μController Fan Control Engine
- PECI 1.1, x2 CPU, x4 domain, C3/C4
- PCH Temp Monitoring
- AMD SB-TSI
- 2 SMBus Interfaces (master or slave)
- IEEE 1284, EPP, ECP, and IBM PC/AT Compatible Parallel Port
- Two 16C550A UART-compatible serial ports
- Floppy disk controller
- 4 PWM Outputs
- 4 fan tachometer inputs
- Programmable automatic fan control support
- Bi-directional PROCHOT# pin support
