The PM5384 S/UNI-1x155 is a single-chip ATM and Packet over SONET/SDH PHY solution.
Applications • Routers and Layer 3 Switches • 3G Wireless Base Station Controllers • DSLAM Uplinks • WAN and Edge ATM switches • LAN switches and hubs • Packet switches and hubs • Network Interface Cards and Uplinks
Additional Features
Single chip ATM and Packet over SONET/SDH Physical Layer Device operating at 155.52 Mbit/s
Implements the ATM Forum User Network Interface (UNI) and the ATM physical layer for Broadband ISDN according to ITU Recommendation I.432
Implements Point-to-Point Protocol (PPP) over SONET/SDH according to RFC 2615
Processes duplex bit-serial 155.52 Mbit/s STS-3c/STM-1 data streams with on-chip clock and data recovery and clock synthesis
Complies with Bellcore GR-253-CORE (2000 Issue) jitter tolerance, jitter transfer (1995 issue), and intrinsic jitter criteria. Provides control circuitry required to comply with Bellcore GR-253-CORE WAN clocking requirements related to wander transfer, holdover, and longterm stability when using an external VCXO
Provides a UTOPIA Level 2, 8-bit wide system interface (clocked up to 52 MHz) with parity support for ATM applications
Provides a UTOPIA Level 2, 16-bit wide system interface (clocked up to 52 MHz) with parity support for ATM applications
Provides a SATURN POS-PHY Level 2, 16-bit system interface (clocked up to 52 MHz) for Packet over SONET/SDH (POS) applications (similar to UTOPIA Level 2, but adapted for packet transfer)
Provides support functions for 1+1 APS operation
Provides a standard 5-signal IEEE 1149.1 JTAG test port for boundary scan board test purposes.
Provides a generic 8-bit microprocessor bus interface for configuration, control, and status monitoring
Low power 2.5/3.3 V CMOS with 5 V TTL-compatible digital inputs/outputs (PECL inputs/outputs are 3.3 V and 5 V compatible)
Industrial temperature range (-40°C to +85°C)
15 mm x15 mm 196-pin stPBGA package with 1 mm ball pitch
The PM5384 S/UNI-1x155 is a single-chip ATM and Packet over SONET/SDH PHY solution.
Applications
• Routers and Layer 3 Switches
• 3G Wireless Base Station Controllers
• DSLAM Uplinks
• WAN and Edge ATM switches
• LAN switches and hubs
• Packet switches and hubs
• Network Interface Cards and Uplinks
Additional Features
- Single chip ATM and Packet over SONET/SDH Physical Layer Device operating at 155.52 Mbit/s
- Implements the ATM Forum User Network Interface (UNI) and the ATM physical layer for Broadband ISDN according to ITU Recommendation I.432
- Implements Point-to-Point Protocol (PPP) over SONET/SDH according to RFC 2615
- Processes duplex bit-serial 155.52 Mbit/s STS-3c/STM-1 data streams with on-chip clock and data recovery and clock synthesis
- Complies with Bellcore GR-253-CORE (2000 Issue) jitter tolerance, jitter transfer (1995 issue), and intrinsic jitter criteria. Provides control circuitry required to comply with Bellcore GR-253-CORE WAN clocking requirements related to wander transfer, holdover, and longterm stability when using an external VCXO
- Provides a UTOPIA Level 2, 8-bit wide system interface (clocked up to 52 MHz) with parity support for ATM applications
- Provides a UTOPIA Level 2, 16-bit wide system interface (clocked up to 52 MHz) with parity support for ATM applications
- Provides a SATURN POS-PHY Level 2, 16-bit system interface (clocked up to 52 MHz) for Packet over SONET/SDH (POS) applications (similar to UTOPIA Level 2, but adapted for packet transfer)
- Provides support functions for 1+1 APS operation
- Provides a standard 5-signal IEEE 1149.1 JTAG test port for boundary scan board test purposes.
- Provides a generic 8-bit microprocessor bus interface for configuration, control, and status monitoring
- Low power 2.5/3.3 V CMOS with 5 V TTL-compatible digital inputs/outputs (PECL inputs/outputs are 3.3 V and 5 V compatible)
- Industrial temperature range (-40°C to +85°C)
- 15 mm x15 mm 196-pin stPBGA package with 1 mm ball pitch
